sm.fit.summary

用VHDL 语言描述频率计的设计

Fitter Status : Successful - Sun Jun 17 22:28:37 2007
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : SM
Top-level Entity Name : SM
Family : Cyclone
Device : EP1C3T144C8
Timing Models : Final
Total logic elements : 7 / 2,910 ( < 1 % )
Total pins : 12 / 104 ( 12 % )
Total virtual pins : 0
Total memory bits : 0 / 59,904 ( 0 % )
Total PLLs : 0 / 1 ( 0 % )