testfre.vhd

用VHDL 语言描述频率计的设计

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TESTFRE IS
 PORT(CLKK:IN STD_LOGIC;
      ENC:OUT STD_LOGIC;
      RSTC:OUT STD_LOGIC;
      LOADC:OUT STD_LOGIC);
END ENTITY;
ARCHITECTURE ONE OF TESTFRE IS
  SIGNAL div2clk:STD_LOGIC;
BEGIN 
  PROCESS(CLKK)
    BEGIN
      IF CLKK'EVENT AND CLKK='1'THEN
          div2clk<=NOT div2clk;
      END IF;
  END PROCESS;
  PROCESS(CLKK,div2clk)
    BEGIN 
      IF CLKK='0'AND div2clk='0'THEN RSTC<='1';
      ELSE RSTC<='0';
      END IF;
    LOADC<=NOT div2clk;
    ENC<=div2clk;
  END PROCESS;
  END ONE;