segdisp.vhd

数码管显示有片选 模块 四输入

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity segdisp is
  port(
       a,b,c,d: in std_logic_vector(3 downto 0);
       clk,rst: in std_logic;
       selout: out std_logic_vector(2 downto 0);
       segout: out std_logic_vector(6 downto 0)
      );
end segdisp;

architecture a of segdisp is
--------------component declaration--------------------
  component encoder
    PORT(
      din : in  std_logic_vector(3 downto 0);
      sout: out std_logic_vector(6 downto 0)
         );
  end component;
-------------------------------------------------------
  signal sel: std_logic_vector(2 downto 0);
  signal b_din: std_logic_vector(3 downto 0);
  signal b_sout: std_logic_vector(6 downto 0);
begin

---------------------counter------------------------
p1:process(clk,rst)
begin
  if rst='1' then
    sel<="111";
  elsif clk'event and clk='1' then
    if sel="100" then
      sel<="111";
    else
      sel<=sel-1;
    end if;
  end if;
end process p1;

selout<=sel;

--------------------statemachine,select the input of the encoder------------------
p2:process(a,b,c,d,sel)
begin
  if rst='1' then
    b_din<="0000";
  else
    case sel is
      when "111" => b_din<=a;
      when "110" => b_din<=b;
      when "101" => b_din<=c;
      when "100" => b_din<=d;
      when others=>null;
    end case;
  end if;
end process p2;

U0: encoder port map(b_din,b_sout);

segout<=b_sout;
end a;


------------component encoder discription--------------------------
library ieee;
use ieee.std_logic_1164.all;

entity encoder is
  port(
      din : in  std_logic_vector(3 downto 0);
      sout: out std_logic_vector(0 to 6)
      );
end encoder;

architecture a of encoder is
begin
  sout<= "1111110" when din="0000" else
	     "0110000" when din="0001" else
	   	 "1101101" when din="0010" else
	     "1111001" when din="0011" else
	     "0110011" when din="0100" else
	     "1011011" when din="0101" else
	     "1011111" when din="0110" else
	     "1110000" when din="0111" else
	     "1111111" when din="1000" else
	     "1111011" when din="1001" else
	     "1110111" when din="1010" else
	     "0011111" when din="1011" else
	     "1001110" when din="1100" else
	     "0111101" when din="1101" else
	     "1001111" when din="1110" else
	     "1000111" when din="1111" else
		 "0000000";
end a;