colsel_g.vhd

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---design to genarate column selection signals

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity colsel_g is
  port(
       clk,rst: in std_logic;
       colselout: out std_logic_vector(3 downto 0)       
       );
end colsel_g;

architecture a of colsel_g is
begin
  process(clk)
  variable temp: std_logic_vector(3 downto 0);
  begin
    if rst='1' then
      temp:="0000";
    elsif clk'event and clk='1' then
      if temp="1111" then 
        temp:="0000";
      else
        temp:=temp+1;
      end if;
    end if;
    colselout<=temp;
  end process;
end a;