📄 se_pa.syr
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Release 8.1i - xst I.24Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.--> Parameter TMPDIR set to ./xst/projnav.tmpCPU : 0.00 / 1.54 s | Elapsed : 0.00 / 2.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 1.54 s | Elapsed : 0.00 / 2.00 s --> Reading design: se_pa.prjTABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) HDL Analysis 4) HDL Synthesis 4.1) HDL Synthesis Report 5) Advanced HDL Synthesis 5.1) Advanced HDL Synthesis Report 6) Low Level Synthesis 7) Final Report=========================================================================* Synthesis Options Summary *=========================================================================---- Source ParametersInput File Name : "se_pa.prj"Input Format : mixedIgnore Synthesis Constraint File : NO---- Target ParametersOutput File Name : "se_pa"Output Format : NGCTarget Device : XC9500 CPLDs---- Source OptionsTop Module Name : se_paAutomatic FSM Extraction : YESFSM Encoding Algorithm : AutoMux Extraction : YESResource Sharing : YES---- Target OptionsAdd IO Buffers : YESMACRO Preserve : YESXOR Preserve : YESEquivalent register Removal : YES---- General OptionsOptimization Goal : SpeedOptimization Effort : 1Keep Hierarchy : YESRTL Output : YesHierarchy Separator : /Bus Delimiter : <>Case Specifier : maintain---- Other Optionslso : se_pa.lsoverilog2001 : YESsafe_implementation : Nowysiwyg : NO==================================================================================================================================================* HDL Compilation *=========================================================================Compiling verilog file "se_pa.v" in library workModule <se_pa> compiledNo errors in compilationAnalysis of file <"se_pa.prj"> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <se_pa>.Module <se_pa> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <se_pa>. Related source file is "se_pa.v". Found 4-bit register for signal <pa_out>. Found 33-bit comparator lessequal for signal <$n0006> created at line 32. Found 33-bit comparator greater for signal <$n0008> created at line 32. Found 32-bit up counter for signal <i>. Summary: inferred 1 Counter(s). inferred 4 D-type flip-flop(s). inferred 2 Comparator(s).Unit <se_pa> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Counters : 1 32-bit up counter : 1# Registers : 4 1-bit register : 4# Comparators : 2 33-bit comparator greater : 1 33-bit comparator lessequal : 1==================================================================================================================================================* Advanced HDL Synthesis *==================================================================================================================================================Advanced HDL Synthesis ReportMacro Statistics# Counters : 1 32-bit up counter : 1# Registers : 36 Flip-Flops : 36==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <se_pa> ... implementation constraint: INIT=r : i_31 implementation constraint: INIT=r : i_0 implementation constraint: INIT=r : i_1 implementation constraint: INIT=r : i_2 implementation constraint: INIT=r : i_3 implementation constraint: INIT=r : i_4 implementation constraint: INIT=r : i_5 implementation constraint: INIT=r : i_6 implementation constraint: INIT=r : i_7 implementation constraint: INIT=r : i_8 implementation constraint: INIT=r : i_9 implementation constraint: INIT=r : i_10 implementation constraint: INIT=r : i_11 implementation constraint: INIT=r : i_12 implementation constraint: INIT=r : i_13 implementation constraint: INIT=r : i_14 implementation constraint: INIT=r : i_15 implementation constraint: INIT=r : i_16 implementation constraint: INIT=r : i_17 implementation constraint: INIT=r : i_18 implementation constraint: INIT=r : i_19 implementation constraint: INIT=r : i_20 implementation constraint: INIT=r : i_21 implementation constraint: INIT=r : i_22 implementation constraint: INIT=r : i_23 implementation constraint: INIT=r : i_24 implementation constraint: INIT=r : i_25 implementation constraint: INIT=r : i_26 implementation constraint: INIT=r : i_27 implementation constraint: INIT=r : i_28 implementation constraint: INIT=r : i_29 implementation constraint: INIT=r : i_30=========================================================================* Final Report *=========================================================================Final ResultsRTL Top Level Output File Name : se_pa.ngrTop Level Output File Name : se_paOutput Format : NGCOptimization Goal : SpeedKeep Hierarchy : YESTarget Technology : XC9500 CPLDsMacro Preserve : YESXOR Preserve : YESwysiwyg : NODesign Statistics# IOs : 7Cell Usage :# BELS : 264# AND2 : 106# AND4 : 2# AND5 : 1# AND8 : 3# INV : 73# OR2 : 41# OR3 : 1# OR4 : 1# OR5 : 1# OR8 : 3# XOR2 : 32# FlipFlops/Latches : 36# FD : 32# FDC : 4# IO Buffers : 7# IBUF : 3# OBUF : 4=========================================================================CPU : 24.04 / 25.66 s | Elapsed : 24.00 / 26.00 s --> Total memory usage is 84424 kilobytesNumber of errors : 0 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)⌨️ 快捷键说明
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