se_pa.srr

这是我自己写的4位并转串ISE代码

#Build: Synplify Pro 8.6.1, Build 013R, Jun  5 2006
#install: D:\Software\Synplify v8.6\fpga_861
#OS: Windows XP 5.1
#Hostname: UESTC-XDK

#Tue Nov 07 08:44:42 2006

$ Start of Compile
#Tue Nov 07 08:44:42 2006

Synplicity Verilog Compiler, version 3.6t, Build 139R, built Jun 15 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved

@I::"D:\Software\Synplify v8.6\fpga_861\lib\xilinx\unisim.v"
@I::"D:\Homework\ISE8.1 work\pa_ser\pa_se.v"
@I::"D:\Homework\ISE8.1 work\pa_ser\se_pa.v"
Verilog syntax check successful!
Selecting top level module se_pa
@N: CG364 :"D:\Homework\ISE8.1 work\pa_ser\se_pa.v":21:7:21:11|Synthesizing module se_pa

@N: CG179 :"D:\Homework\ISE8.1 work\pa_ser\se_pa.v":39:15:39:20|Removing redundant assignment
@W: CL112 :"D:\Homework\ISE8.1 work\pa_ser\se_pa.v":28:2:28:7|Feedback mux created for signal i[31:0]. Did you forget the set/reset assignment for this signal?
@W: CL189 :"D:\Homework\ISE8.1 work\pa_ser\se_pa.v":28:2:28:7|Register bit i[31] is always 0, optimizing ...
@W: CL171 :"D:\Homework\ISE8.1 work\pa_ser\se_pa.v":28:2:28:7|Pruning Register bit <31> of i[31:0] 

@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Nov 07 08:44:44 2006

###########################################################]
###########################################################[
Synplicity Xilinx Technology Mapper, Version 8.6.0, Build 246R, Built Jun 20 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved
Version 8.6.1
@N: MF249 |Running in 32-bit mode.
@N: MF258 |Gated clock conversion disabled 


RTL optimization done.

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 30MB)
Automatic dissolve during optimization of view:work.se_pa(verilog) of i_1_1(PM_ADDC__0_3_xc9536)

Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)

Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)

Clock Buffers:
  Inserting Clock buffer for port clk[0],	TNM=clk_0_


Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)

Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)

Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
------------------------------------------------------------


Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
@N: FX164 |The option to pack flops in the IOB has not been specified 
Total number of merged luts: 0

Finished restoring hierarchy (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
@N: BN191 |Writing property annotation file D:\Homework\ISE8.1 work\pa_ser\rev_1\se_pa.tap.
Writing Analyst data base D:\Homework\ISE8.1 work\pa_ser\rev_1\se_pa.srm
@N: BN225 |Writing default property annotation file D:\Homework\ISE8.1 work\pa_ser\rev_1\se_pa.map.
Writing EDIF Netlist and constraint files
Version 8.6.1
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
---------------------------------------
Resource Usage Report for se_pa 

Mapping to part: xc9536vq44-5
Simple gate primitives:
AND2            14 uses
AND2B1          6 uses
FD              31 uses
FDC             4 uses
OR2             34 uses
XOR2            2 uses

I/O ports: 7
I/O primitives: 6
IBUF           2 uses
OBUF           4 uses

BUFG           1 use

I/O Register bits:                  0
Register bits not including I/Os:   35

Mapper successful!
Process took 0h:00m:02s realtime, 0h:00m:01s cputime
# Tue Nov 07 08:44:47 2006

###########################################################]