se_pa.tlg

这是我自己写的4位并转串ISE代码

Selecting top level module se_pa
@N: CG364 :"D:\Homework\ISE8.1 work\pa_ser\se_pa.v":21:7:21:11|Synthesizing module se_pa

@N: CG179 :"D:\Homework\ISE8.1 work\pa_ser\se_pa.v":39:15:39:20|Removing redundant assignment
@W: CL112 :"D:\Homework\ISE8.1 work\pa_ser\se_pa.v":28:2:28:7|Feedback mux created for signal i[31:0]. Did you forget the set/reset assignment for this signal?
@W: CL189 :"D:\Homework\ISE8.1 work\pa_ser\se_pa.v":28:2:28:7|Register bit i[31] is always 0, optimizing ...
@W: CL171 :"D:\Homework\ISE8.1 work\pa_ser\se_pa.v":28:2:28:7|Pruning Register bit <31> of i[31:0]