📄 pa_se_srr.htm
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<!@TC:1162819048>
#Build: Synplify Pro 8.6.1, Build 013R, Jun 5 2006
#install: D:\Software\Synplify v8.6\fpga_861
#OS: Windows XP 5.1
#Hostname: UESTC-XDK
#Mon Nov 06 21:17:22 2006
<a name=compilerReport1>$ Start of Compile
#Mon Nov 06 21:17:22 2006
Synplicity Verilog Compiler, version 3.6t, Build 139R, built Jun 15 2006
Copyright (C) 1994-2006, Synplicity Inc. All Rights Reserved
@I::"D:\Software\Synplify v8.6\fpga_861\lib\xilinx\unisim.v"
@I::"D:\Homework\ISE8.1 work\pa_ser\se_pa.v"
@I::"D:\Homework\ISE8.1 work\pa_ser\pa_se.v"
Verilog syntax check successful!
Compiler output is up to date. No re-compile necessary
Selecting top level module pa_se
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="d:\homework\ise8.1 work\pa_ser\pa_se.v:21:7:21:12:@N:CG364:@XP_MSG">pa_se.v(21)</a><!@TM:1162819048> | Synthesizing module pa_se
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="d:\homework\ise8.1 work\pa_ser\pa_se.v:39:12:39:15:@N:CG179:@XP_MSG">pa_se.v(39)</a><!@TM:1162819048> | Removing redundant assignment
<font color=#A52A2A>@W:<a href="@W:CL112:@XP_HELP">CL112</a> : <a href="d:\homework\ise8.1 work\pa_ser\pa_se.v:29:4:29:10:@W:CL112:@XP_MSG">pa_se.v(29)</a><!@TM:1162819048> | Feedback mux created for signal i[31:0]. Did you forget the set/reset assignment for this signal?</font>
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Nov 06 21:17:23 2006
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<a name=mapperReport2>Synplicity Xilinx Technology Mapper, Version 8.6.0, Build 246R, Built Jun 20 2006
Copyright (C) 1994-2006, Synplicity Inc. All Rights Reserved
Version 8.6.1
@N:<a href="@N:MF249:@XP_HELP">MF249</a> : <!@TM:1162819048> | Running in 32-bit mode.
@N:<a href="@N:MF258:@XP_HELP">MF258</a> : <!@TM:1162819048> | Gated clock conversion disabled
RTL optimization done.
Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 30MB)
@N: : <a href="d:\homework\ise8.1 work\pa_ser\pa_se.v:29:4:29:10:@N::@XP_MSG">pa_se.v(29)</a><!@TM:1162819048> | Found counter in view:work.pa_se(verilog) inst i[31:0]
Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 32MB)
Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 32MB)
Clock Buffers:
Inserting Clock buffer for port clk[0], TNM=clk_0_
Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 32MB)
Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 32MB)
Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 32MB)
Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 32MB)
Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 32MB)
Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 32MB)
Pass CPU time Worst Slack Luts / Registers
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Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
------------------------------------------------------------
Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 32MB)
@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1162819048> | The option to pack flops in the IOB has not been specified
Total number of merged luts: 0
Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 32MB)
@N:<a href="@N:BN191:@XP_HELP">BN191</a> : <!@TM:1162819048> | Writing property annotation file D:\Homework\ISE8.1 work\pa_ser\rev_1\pa_se.tap.
Writing Analyst data base D:\Homework\ISE8.1 work\pa_ser\rev_1\pa_se.srm
@N:<a href="@N:BN225:@XP_HELP">BN225</a> : <!@TM:1162819048> | Writing default property annotation file D:\Homework\ISE8.1 work\pa_ser\rev_1\pa_se.map.
Writing EDIF Netlist and constraint files
Version 8.6.1
@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1162819048> | Timing Report not generated for this device, please use place and route tools for timing analysis.
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<a name=resourceUsage3>Resource Usage Report for pa_se
Mapping to part: xc9536vq44-5
Simple gate primitives:
AND2 18 uses
AND2B1 4 uses
FD 32 uses
FDC 1 use
OR2 63 uses
XOR2 30 uses
I/O ports: 7
I/O primitives: 6
IBUF 5 uses
OBUF 1 use
BUFG 1 use
I/O Register bits: 0
Register bits not including I/Os: 33
Mapper successful!
Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Mon Nov 06 21:17:27 2006
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