pa_se_tst.ant

这是我自己写的4位并转串ISE代码

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2003 Xilinx, Inc.
// All Right Reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /    Vendor: Xilinx 
// \   \   \/     Version : 8.1i
//  \   \         Application : ISE
//  /   /         Filename : pa_se_tst.ant
// /___/   /\     Timestamp : Mon Oct 30 09:07:21 2006
// \   \  /  \ 
//  \___\/\___\ 
//
//Command: 
//Design Name: pa_se_tst
//Device: Xilinx
//
`timescale 1ns/1ps

module pa_se_tst;
    reg clk = 1'b0;
    reg [3:0] in = 4'b1101;
    wire out;
    reg clr = 1'b0;

    parameter PERIOD = 200;
    parameter real DUTY_CYCLE = 0.5;
    parameter OFFSET = 0;

    initial    // Clock process for clk
    begin
        #OFFSET;
        forever
        begin
            clk = 1'b0;
            #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
            #(PERIOD*DUTY_CYCLE);
        end
    end

    pa_se UUT (
        .clk(clk),
        .in(in),
        .out(out),
        .clr(clr));

    integer TX_FILE = 0;
    integer TX_ERROR = 0;
    
    initial begin    // Annotation process for clock clk
        #0;
        ANNOTATE_out;
        #OFFSET;
        forever begin
            #120;
            ANNOTATE_out;
            #80;
        end
    end

    initial begin  // Open the annotations file...
        TX_FILE = $fopen("D:\\Homework\\ISE8.1 work\\pa_ser\\pa_se_tst.ano");
        #1200 // Final time:  1200 ns
        $display("Success! Annotation Simulation Complete.");
        $fdisplay(TX_FILE, "Total[%d]", TX_ERROR);
        $fclose(TX_FILE);
        $finish;
    end

    initial begin
        // -------------  Current Time:  80ns
        #80;
        clr = 1'b1;
        // -------------------------------------
    end

    task ANNOTATE_out;
        #0 begin
            $fdisplay(TX_FILE, "Annotate[%d,out,%b]", $time, out);
            $fflush(TX_FILE);
            TX_ERROR = TX_ERROR + 1;
        end
    endtask

endmodule