se_pa_sy.prj

这是我自己写的4位并转串ISE代码

#-- Synplicity, Inc.
#-- Version Synplify Pro 8.6.1
#-- Project file D:\Homework\ISE8.1 work\pa_ser\se_pa_sy.prj
#-- Written on Tue Nov 07 08:44:42 2006


#add_file options
add_file -verilog "pa_se.v"
add_file -verilog "se_pa.v"


#implementation: "rev_1"
impl -add rev_1 -type fpga

#device options
set_option -technology XC9500
set_option -part XC9536
set_option -package VQ44
set_option -speed_grade -5

#compilation/mapping options
set_option -default_enum_encoding sequential
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1

#map options
set_option -frequency 1.000
set_option -run_prop_extract 1
set_option -fanout_limit 100
set_option -disable_io_insertion 0
set_option -verification_mode 0
set_option -no_sequential_opt 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#VIF options
set_option -write_vif 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "rev_1/se_pa.edf"

#
#implementation attributes

set_option -vlog_std v2001
set_option -dup 0
set_option -project_relative_includes 1
impl -active "rev_1"