_primary.vhd

来自「这是我自己写的4位并转串ISE代码」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity se_pa is
    port(
        se_in           : in     vl_logic_vector(0 downto 0);
        pa_out          : out    vl_logic_vector(3 downto 0);
        clr             : in     vl_logic_vector(0 downto 0);
        clk             : in     vl_logic_vector(0 downto 0)
    );
end se_pa;