mult_tst.v

这是我自己写的两个8位二进制数的乘法程序

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   22:16:31 11/06/2006
// Design Name:   Mult
// Module Name:   Mult_tst.v
// Project Name:  Mult
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Mult
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module Mult_tst_v;

	// Inputs
	reg [7:0] a;
	reg [7:0] b;

	// Outputs
	wire [15:0] out;

	// Instantiate the Unit Under Test (UUT)
	Mult uut (
		.a(a), 
		.b(b), 
		.out(out)
	);

	initial begin
		// Initialize Inputs
		a = 0;
		b = 0;

		// Wait 100 ns for global reset to finish
		#100 b=8'd225;
		#100 a=8'd110;
		#100 a=8'd220;b=8'd4;
		#100 a=8'd11;b=8'd11;
		#100 a=8'd130;b=8'd3;
		#100 a=8'd200;b=8'd130;
		#100 a=8'd180;b=8'd225;
		#100 a=8'd15;b=8'd15;
		#100 $finish;
		
        
		// Add stimulus here

	end
      
endmodule