sub_tst.v

这是我自己写的两个8位二进制数的乘法程序

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   17:41:32 11/07/2006
// Design Name:   sub_cf
// Module Name:   SUB_tst.v
// Project Name:  Mult
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: sub_cf
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module SUB_tst_v;

	// Inputs
	reg [3:0] a;
	reg [3:0] b;

	// Outputs
	wire [3:0] out;
	wire CF;

	// Instantiate the Unit Under Test (UUT)
	sub_cf uut (
		.a(a), 
		.b(b), 
		.out(out), 
		.CF(CF)
	);

	initial begin
		// Initialize Inputs
		a = 0;
		b = 0;

		// Wait 100 ns for global reset to finish
		#100 b=4'd3;
		#100 a=4'd2;b=4'd1;
		#100 a=4'd10;b=4'd5;
		#100 a=4'd7;b=4'd4;
		#100 a=4'd15;b=4'd10;
      #100 a=4'd13;b=4'd9;
      #100 a=4'd12;b=4'd6;
      #100 a=4'd8;b=4'd9;
      #100 a=4'd9;b=4'd8;
      #100 a=4'd14;b=4'd15;
      #100 a=4'd15;b=4'd0;
      #100 a=4'd7;b=4'd7;
      #100 $finish; 
      
        
		// Add stimulus here

	end
      
endmodule