mult_tst.srs

这是我自己写的两个8位二进制数的乘法程序

#
#
#
# Created by Synplify Verilog HDL Compiler version 3.6t, Build 139R from Synplicity, Inc.
# Copyright 1994-2006 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Tue Nov 07 08:49:55 2006
#
#
#OPTIONS:"|-nram|-divnmod|-I|D:\\Homework\\ISE8.1 work\\Mult\\|-I|D:\\Software\\Synplify v8.6\\fpga_861\\lib|-v2001|-devicelib|D:\\Software\\Synplify v8.6\\fpga_861\\lib\\xilinx\\unisim.v|-autosm|-fid2|-sharing|on|-encrypt|-ui|-pro|-ram|-ll|2000"
#CUR:"D:\\Software\\Synplify v8.6\\fpga_861\\bin\\c_ver.exe":1150348450
#CUR:"D:\\Software\\Synplify v8.6\\fpga_861\\lib\\xilinx\\unisim.v":1150356194
#CUR:"D:\\Software\\Synplify v8.6\\fpga_861\\lib\\xilinx\\unisim.v":1150356194
#CUR:"D:\\Homework\\ISE8.1 work\\Mult\\Mul.v":1162859756
#CUR:"D:\\Homework\\ISE8.1 work\\Mult\\Mul.v":1162859756
#CUR:"D:\\Homework\\ISE8.1 work\\Mult\\Mult_tst.v":1162859852
#CUR:"D:\\Homework\\ISE8.1 work\\Mult\\Mult_tst.v":1162859852
f "D:\Software\Synplify v8.6\fpga_861\lib\xilinx\unisim.v"; # file 0
af .is_verilog 1;
f "D:\Homework\ISE8.1 work\Mult\Mul.v"; # file 1
af .is_verilog 1;
f "D:\Homework\ISE8.1 work\Mult\Mult_tst.v"; # file 2
af .is_verilog 1;
@E
@ 
ftell;
@E@MR@..:6::(.46:nFRIsv	Rk_D00_#0PCRPsFHDoN;
PHR3#sPCHoDFR
4;N3PRHP#_CDsHF4oR;P
NRs3FHNohl"CRv0kD_00#_;P"
@bR@4j::44::0.RsRkC0CskRk0sCb;
Rj@@:44::.4:RDVN#VCRNCD#RDVN#
C;C
;