mult_tst.srr

这是我自己写的两个8位二进制数的乘法程序

#Build: Synplify Pro 8.6.1, Build 013R, Jun  5 2006
#install: D:\Software\Synplify v8.6\fpga_861
#OS: Windows XP 5.1
#Hostname: UESTC-XDK

#Tue Nov 07 08:49:54 2006

$ Start of Compile
#Tue Nov 07 08:49:54 2006

Synplicity Verilog Compiler, version 3.6t, Build 139R, built Jun 15 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved

@I::"D:\Software\Synplify v8.6\fpga_861\lib\xilinx\unisim.v"
@I::"D:\Homework\ISE8.1 work\Mult\Mul.v"
@I::"D:\Homework\ISE8.1 work\Mult\Mult_tst.v"
Verilog syntax check successful!
Selecting top level module Mult_tst_v
@N: CG364 :"D:\Homework\ISE8.1 work\Mult\Mul.v":21:7:21:10|Synthesizing module Mult

@N: CG179 :"D:\Homework\ISE8.1 work\Mult\Mul.v":35:17:35:19|Removing redundant assignment
@N: CG364 :"D:\Homework\ISE8.1 work\Mult\Mult_tst.v":25:7:25:16|Synthesizing module Mult_tst_v

@W: CG293 :"D:\Homework\ISE8.1 work\Mult\Mult_tst.v":41:1:41:7|Ignoring initial statement
@W: CG439 :"D:\Homework\ISE8.1 work\Mult\Mult_tst.v":41:1:41:7|Initial statement will only initialize memories through the usage of $readmemh and $readmemb
@W: CG133 :"D:\Homework\ISE8.1 work\Mult\Mult_tst.v":28:11:28:11|No assignment to a
@W: CG133 :"D:\Homework\ISE8.1 work\Mult\Mult_tst.v":29:11:29:11|No assignment to b
@W: CL168 :"D:\Homework\ISE8.1 work\Mult\Mult_tst.v":35:6:35:8|Pruning instance uut - not in use ...

@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Nov 07 08:49:55 2006

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Synplicity Xilinx Technology Mapper, Version 8.6.0, Build 246R, Built Jun 20 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved
Version 8.6.1
@N: MF249 |Running in 32-bit mode.
@N: MF258 |Gated clock conversion disabled 


RTL optimization done.

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 30MB)

Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 30MB)

Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 30MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 30MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 30MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 30MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 30MB)

Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 30MB)

Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 30MB)
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
------------------------------------------------------------


Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 30MB)
@N: FX164 |The option to pack flops in the IOB has not been specified 
Total number of merged luts: 0

Finished restoring hierarchy (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 30MB)
@N: BN191 |Writing property annotation file D:\Homework\ISE8.1 work\Mult\rev_2\Mult_tst.tap.
Writing Analyst data base D:\Homework\ISE8.1 work\Mult\rev_2\Mult_tst.srm
@N: BN225 |Writing default property annotation file D:\Homework\ISE8.1 work\Mult\rev_2\Mult_tst.map.
Writing EDIF Netlist and constraint files
Version 8.6.1
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
---------------------------------------
Resource Usage Report for Mult_tst_v 

Mapping to part: xc9536vq44-5
I/O Register bits:                  0
Register bits not including I/Os:   0

Mapper successful!
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Nov 07 08:49:59 2006

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