📄 mul_srr.htm
字号:
<html>
<body><samp><pre>
<!@TC:1162902976>
#Build: Synplify Pro 8.6.1, Build 013R, Jun 5 2006
#install: D:\Software\Synplify v8.6\fpga_861
#OS: Windows XP 5.1
#Hostname: UESTC-XDK
#Tue Nov 07 20:36:02 2006
<a name=compilerReport1>$ Start of Compile
#Tue Nov 07 20:36:02 2006
Synplicity Verilog Compiler, version 3.6t, Build 139R, built Jun 15 2006
Copyright (C) 1994-2006, Synplicity Inc. All Rights Reserved
@I::"D:\Software\Synplify v8.6\fpga_861\lib\xilinx\unisim.v"
@I::"D:\Homework\ISE8.1 work\Mult\Mul.v"
Verilog syntax check successful!
Compiler output is up to date. No re-compile necessary
Selecting top level module Mult
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="d:\homework\ise8.1 work\mult\mul.v:21:7:21:11:@N:CG364:@XP_MSG">mul.v(21)</a><!@TM:1162902976> | Synthesizing module Mult
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="d:\homework\ise8.1 work\mult\mul.v:35:17:35:20:@N:CG179:@XP_MSG">mul.v(35)</a><!@TM:1162902976> | Removing redundant assignment
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Nov 07 20:36:03 2006
###########################################################]
###########################################################[
<a name=mapperReport2>Synplicity Xilinx Technology Mapper, Version 8.6.0, Build 246R, Built Jun 20 2006
Copyright (C) 1994-2006, Synplicity Inc. All Rights Reserved
Version 8.6.1
@N:<a href="@N:MF249:@XP_HELP">MF249</a> : <!@TM:1162902976> | Running in 32-bit mode.
@N:<a href="@N:MF258:@XP_HELP">MF258</a> : <!@TM:1162902976> | Gated clock conversion disabled
RTL optimization done.
Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 30MB)
Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 32MB)
Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 32MB)
Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:02s; Memory used current: 32MB peak: 32MB)
Starting Early Timing Optimization (Time elapsed 0h:00m:02s; Memory used current: 32MB peak: 32MB)
Finished Early Timing Optimization (Time elapsed 0h:00m:02s; Memory used current: 32MB peak: 32MB)
Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:02s; Memory used current: 32MB peak: 32MB)
Finished preparing to map (Time elapsed 0h:00m:02s; Memory used current: 32MB peak: 32MB)
Finished technology mapping (Time elapsed 0h:00m:02s; Memory used current: 31MB peak: 32MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
------------------------------------------------------------
Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:02s; Memory used current: 31MB peak: 32MB)
@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1162902976> | The option to pack flops in the IOB has not been specified
Total number of merged luts: 0
Finished restoring hierarchy (Time elapsed 0h:00m:02s; Memory used current: 32MB peak: 32MB)
@N:<a href="@N:BN191:@XP_HELP">BN191</a> : <!@TM:1162902976> | Writing property annotation file D:\Homework\ISE8.1 work\Mult\rev_2\Mul.tap.
Writing Analyst data base D:\Homework\ISE8.1 work\Mult\rev_2\Mul.srm
@N:<a href="@N:BN225:@XP_HELP">BN225</a> : <!@TM:1162902976> | Writing default property annotation file D:\Homework\ISE8.1 work\Mult\rev_2\Mul.map.
Writing EDIF Netlist and constraint files
Version 8.6.1
@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1162902976> | Timing Report not generated for this device, please use place and route tools for timing analysis.
---------------------------------------
<a name=resourceUsage3>Resource Usage Report for Mult
Mapping to part: xc9536vq44-5
Simple gate primitives:
AND2 167 uses
AND2B1 55 uses
OR2 145 uses
XOR2 104 uses
I/O ports: 32
I/O primitives: 32
IBUF 16 uses
OBUF 16 uses
I/O Register bits: 0
Register bits not including I/Os: 0
Mapper successful!
Process took 0h:00m:10s realtime, 0h:00m:04s cputime
# Tue Nov 07 20:36:15 2006
###########################################################]
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -