📄 mult_tst_srr.htm
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<!@TC:1162860600>
#Build: Synplify Pro 8.6.1, Build 013R, Jun 5 2006
#install: D:\Software\Synplify v8.6\fpga_861
#OS: Windows XP 5.1
#Hostname: UESTC-XDK
#Tue Nov 07 08:49:54 2006
<a name=compilerReport1>$ Start of Compile
#Tue Nov 07 08:49:54 2006
Synplicity Verilog Compiler, version 3.6t, Build 139R, built Jun 15 2006
Copyright (C) 1994-2006, Synplicity Inc. All Rights Reserved
@I::"D:\Software\Synplify v8.6\fpga_861\lib\xilinx\unisim.v"
@I::"D:\Homework\ISE8.1 work\Mult\Mul.v"
@I::"D:\Homework\ISE8.1 work\Mult\Mult_tst.v"
Verilog syntax check successful!
Selecting top level module Mult_tst_v
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="d:\homework\ise8.1 work\mult\mul.v:21:7:21:11:@N:CG364:@XP_MSG">mul.v(21)</a><!@TM:1162860600> | Synthesizing module Mult
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="d:\homework\ise8.1 work\mult\mul.v:35:17:35:20:@N:CG179:@XP_MSG">mul.v(35)</a><!@TM:1162860600> | Removing redundant assignment
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="d:\homework\ise8.1 work\mult\mult_tst.v:25:7:25:17:@N:CG364:@XP_MSG">mult_tst.v(25)</a><!@TM:1162860600> | Synthesizing module Mult_tst_v
<font color=#A52A2A>@W:<a href="@W:CG293:@XP_HELP">CG293</a> : <a href="d:\homework\ise8.1 work\mult\mult_tst.v:41:1:41:8:@W:CG293:@XP_MSG">mult_tst.v(41)</a><!@TM:1162860600> | Ignoring initial statement</font>
<font color=#A52A2A>@W:<a href="@W:CG439:@XP_HELP">CG439</a> : <a href="d:\homework\ise8.1 work\mult\mult_tst.v:41:1:41:8:@W:CG439:@XP_MSG">mult_tst.v(41)</a><!@TM:1162860600> | Initial statement will only initialize memories through the usage of $readmemh and $readmemb</font>
<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="d:\homework\ise8.1 work\mult\mult_tst.v:28:11:28:12:@W:CG133:@XP_MSG">mult_tst.v(28)</a><!@TM:1162860600> | No assignment to a</font>
<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="d:\homework\ise8.1 work\mult\mult_tst.v:29:11:29:12:@W:CG133:@XP_MSG">mult_tst.v(29)</a><!@TM:1162860600> | No assignment to b</font>
<font color=#A52A2A>@W:<a href="@W:CL168:@XP_HELP">CL168</a> : <a href="d:\homework\ise8.1 work\mult\mult_tst.v:35:6:35:9:@W:CL168:@XP_MSG">mult_tst.v(35)</a><!@TM:1162860600> | Pruning instance uut - not in use ...</font>
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Nov 07 08:49:55 2006
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<a name=mapperReport2>Synplicity Xilinx Technology Mapper, Version 8.6.0, Build 246R, Built Jun 20 2006
Copyright (C) 1994-2006, Synplicity Inc. All Rights Reserved
Version 8.6.1
@N:<a href="@N:MF249:@XP_HELP">MF249</a> : <!@TM:1162860600> | Running in 32-bit mode.
@N:<a href="@N:MF258:@XP_HELP">MF258</a> : <!@TM:1162860600> | Gated clock conversion disabled
RTL optimization done.
Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 30MB)
Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 30MB)
Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 30MB)
Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 30MB)
Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 30MB)
Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 30MB)
Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 30MB)
Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 30MB)
Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 30MB)
Pass CPU time Worst Slack Luts / Registers
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Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
------------------------------------------------------------
Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 30MB)
@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1162860600> | The option to pack flops in the IOB has not been specified
Total number of merged luts: 0
Finished restoring hierarchy (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 30MB)
@N:<a href="@N:BN191:@XP_HELP">BN191</a> : <!@TM:1162860600> | Writing property annotation file D:\Homework\ISE8.1 work\Mult\rev_2\Mult_tst.tap.
Writing Analyst data base D:\Homework\ISE8.1 work\Mult\rev_2\Mult_tst.srm
@N:<a href="@N:BN225:@XP_HELP">BN225</a> : <!@TM:1162860600> | Writing default property annotation file D:\Homework\ISE8.1 work\Mult\rev_2\Mult_tst.map.
Writing EDIF Netlist and constraint files
Version 8.6.1
@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1162860600> | Timing Report not generated for this device, please use place and route tools for timing analysis.
---------------------------------------
<a name=resourceUsage3>Resource Usage Report for Mult_tst_v
Mapping to part: xc9536vq44-5
I/O Register bits: 0
Register bits not including I/Os: 0
Mapper successful!
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Nov 07 08:49:59 2006
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