people4.v

来自「这是我自己写的4人表决器源码」· Verilog 代码 · 共 51 行

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    22:46:12 01/18/2007 
// Design Name: 
// Module Name:    people4 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module people4(a, b, c, d, e);
    input [0:0] a;
    input [0:0] b;
    input [0:0] c;
    input [0:0] d;
    output [0:0] e;
	 reg e;
    always @(a or b or c or d)
	 begin
	   case ({a,b,c,d})
		4'b0000: e<=0;
		4'b0001: e<=0;	
		4'b0010: e<=0;	
		4'b0011: e<=0;	
		4'b0100: e<=0;	
		4'b0101: e<=0;	
		4'b0110: e<=0;	
		4'b0111: e<=1;	
		4'b1000: e<=0;	
		4'b1001: e<=0;	
		4'b1010: e<=0;	
		4'b1011: e<=1;	
		4'b1100: e<=0;	
		4'b1101: e<=1;	
		4'b1110: e<=1;	
		4'b1111: e<=1;
      default: e<=1'bz;		
     endcase
	 end
endmodule