people4.srs

这是我自己写的4人表决器源码

#
#
#
# Created by Synplify Verilog HDL Compiler version 3.6t, Build 139R from Synplicity, Inc.
# Copyright 1994-2006 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Fri Jan 19 10:08:57 2007
#
#
#OPTIONS:"|-top|people4|-primux|-fixsmult|-sdff_counter|-infer_seqShift|-nram|-divnmod|-I|E:\\Homework\\ISE8.1 work\\people4\\|-I|D:\\Software\\Synplify 8.6.1\\fpga_861\\lib|-v2001|-devicelib|D:\\Software\\Synplify 8.6.1\\fpga_861\\lib\\xilinx\\unisim.v|-autosm|-fid2|-sharing|on|-encrypt|-ui|-pro|-ram|-ll|2000"
#CUR:"D:\\Software\\Synplify 8.6.1\\fpga_861\\bin\\c_ver.exe":1150348450
#CUR:"D:\\Software\\Synplify 8.6.1\\fpga_861\\lib\\xilinx\\unisim.v":1150356194
#CUR:"D:\\Software\\Synplify 8.6.1\\fpga_861\\lib\\xilinx\\unisim.v":1150356194
#CUR:"D:\\Software\\Synplify 8.6.1\\fpga_861\\bin\\..\\lib\\xilinx\\unisim.v":1150356194
#CUR:"D:\\Software\\Synplify 8.6.1\\fpga_861\\bin\\..\\lib\\xilinx\\unisim.v":1150356194
#CUR:"E:\\Homework\\ISE8.1 work\\people4\\people4.v":1169168746
#CUR:"E:\\Homework\\ISE8.1 work\\people4\\people4.v":1169168746
f "D:\Software\Synplify 8.6.1\fpga_861\lib\xilinx\unisim.v"; # file 0
af .is_verilog 1;
f "D:\Software\Synplify 8.6.1\fpga_861\bin\..\lib\xilinx\unisim.v"; # file 1
af .is_verilog 1;
f "E:\Homework\ISE8.1 work\people4\people4.v"; # file 2
af .is_verilog 1;
@E
@ 
ftell;
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o;N3PRHC#PsFHDo;R4
RNP3_H#PHCsDRFo4N;
PFR3shHoNRlC"FbCbcDC"
;

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HsR30FD_sMHoNRlC";L"
@HR@..:cn:4::.c4OnRrRj9O9rj;H
NR$3#Ms_NsbN$FRs04N;
HsR30FD_sMHoNRlC";O"
@HR@..:6n:4::.648nRrRj989rj;H
NR$3#Ms_NsbN$FRs04N;
HsR30FD_sMHoNRlC";8"
@FR@..:(::n.n(:RjCr9_RC49rj;H
NR$3#Ms_NsbN$FRs04N;
HsR30FD_sMHoNRlC";C"
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Rj@@:44::.4:RDVN#VCRNCD#RDVN#
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