stdout.log

来自「这是我自己写的4人表决器源码」· LOG 代码 · 共 57 行

License checkout: synplify

Starting:    D:\Software\Synplify 8.6.1\fpga_861\bin\mbin\synplify.exe
Install:     D:\Software\Synplify 8.6.1\fpga_861
Date:        Fri Jan 19 10:08:55 2007
Version:     8.6.1


Arguments:   -batch -splash -launchmode people4.prj -tcl people4_map.tcl
ProductType: synplify

License: synplify node-locked 
Running in Vendor Mode



Running synthesis on people4:people4

log file: "E:\Homework\ISE8.1 work\people4\people4.srr"


Running Verilog Compiler...

Verilog Compiler Completed


Total: 0 errors, 1 warning, 1 note


Running Analysis Property Generator...

Launching mapper in pro mode

Analysis Property Generator Completed


Analysis Property Generator Complete

Total: 0 errors, 1 warning, 1 note


Running SPARTAN3E Mapper...

Launching mapper in pro mode

SPARTAN3E Mapper Completed


Total: 0 errors, 1 warning, 12 notes


TCL script complete: "E:\Homework\ISE8.1 work\people4\people4_map.tcl"

exit status=0