pepole4_tst.v

这是我自己写的4人表决器源码

// Verilog Test Fixture Template

  `timescale 1 ns / 1 ps

  module TEST_gate;
          reg a;
          reg [0:0] b;
          reg [0:0] c;
          reg d;
			 wire e;

          people4 d4 (
                  .a(a),
                  .b(b),
						.c(c),
						.d(d),
						.e(e)
          );



   // The following code initializes the Global Set Reset (GSR) and Global Three-State (GTS) nets
   // Refer to the Synthesis and Simulation Design Guide for more information on this process


   initial begin
      {a,b,c,d}=4'b0000;
      #100 {a,b,c,d}=4'b0000; // GSR is set for 100 ns
      #100 {a,b,c,d}=4'b0001; // GSR is set for 100 ns
      #100 {a,b,c,d}=4'b0010; // GSR is set for 100 ns
      #100 {a,b,c,d}=4'b0011; // GSR is set for 100 ns
      #100 {a,b,c,d}=4'b0100; // GSR is set for 100 ns
      #100 {a,b,c,d}=4'b0101; // GSR is set for 100 ns
      #100 {a,b,c,d}=4'b0110; // GSR is set for 100 ns
      #100 {a,b,c,d}=4'b0111; // GSR is set for 100 ns
      #100 {a,b,c,d}=4'b1000; // GSR is set for 100 ns
      #100 {a,b,c,d}=4'b1001; // GSR is set for 100 ns
      #100 {a,b,c,d}=4'b1010; // GSR is set for 100 ns
      #100 {a,b,c,d}=4'b1011; // GSR is set for 100 ns
      #100 {a,b,c,d}=4'b1100; // GSR is set for 100 ns
      #100 {a,b,c,d}=4'b1101; // GSR is set for 100 ns
      #100 {a,b,c,d}=4'b1110; // GSR is set for 100 ns
      #100 {a,b,c,d}=4'b1111; // GSR is set for 100 ns
      #100 {a,b,c,d}=4'b0000; // GSR is set for 100 ns
      #100 {a,b,c,d}=4'b1101; // GSR is set for 100 ns
      #100 $finish;
      
   end
  endmodule