people4_translate.v

这是我自己写的4人表决器源码

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: I.34
//  \   \         Application: netgen
//  /   /         Filename: people4_translate.v
// /___/   /\     Timestamp: Fri Jan 19 11:24:49 2007
// \   \  /  \ 
//  \___\/\___\
//             
// Command	: -intstyle ise -insert_glbl true -w -dir netgen/translate -ofmt verilog -sim people4.ngd people4_translate.v 
// Device	: 3s500efg320-4
// Input file	: people4.ngd
// Output file	: E:\Homework\ISE8.1 work\people4\netgen\translate\people4_translate.v
// # of Modules	: 1
// Design Name	: people4
// Xilinx        : D:\Software\Xilinx ISE8.2
//             
// Purpose:    
//     This verilog netlist is a verification model and uses simulation 
//     primitives which may not represent the true implementation of the 
//     device, however the netlist is functionally correct and should not 
//     be modified. This file cannot be synthesized and should only be used 
//     with supported simulation tools.
//             
// Reference:  
//     Development System Reference Guide, Chapter 23
//     Synthesis and Simulation Design Guide, Chapter 6
//             
////////////////////////////////////////////////////////////////////////////////

`timescale 1 ns/1 ps

module people4 (
a, b, c, d, e
);
  input [0 : 0] a;
  input [0 : 0] b;
  input [0 : 0] c;
  input [0 : 0] d;
  output [0 : 0] e;
  wire m5_0;
  wire [0 : 0] a_c;
  wire [0 : 0] b_c;
  wire [0 : 0] c_c;
  wire [0 : 0] d_c;
  defparam m5.INIT = 16'hE880;
  X_LUT4 m5 (
    .ADR0(a_c[0]),
    .ADR1(b_c[0]),
    .ADR2(c_c[0]),
    .ADR3(d_c[0]),
    .O(m5_0)
  );
  X_BUF \d_ibuf[0]  (
    .I(d[0]),
    .O(d_c[0])
  );
  X_BUF \c_ibuf[0]  (
    .I(c[0]),
    .O(c_c[0])
  );
  X_BUF \b_ibuf[0]  (
    .I(b[0]),
    .O(b_c[0])
  );
  X_BUF \a_ibuf[0]  (
    .I(a[0]),
    .O(a_c[0])
  );
  defparam \a[0] .LOC = "N17";
  X_IPAD \a[0]  (
    .PAD(a[0])
  );
  defparam \b[0] .LOC = "H18";
  X_IPAD \b[0]  (
    .PAD(b[0])
  );
  defparam \c[0] .LOC = "L14";
  X_IPAD \c[0]  (
    .PAD(c[0])
  );
  defparam \d[0] .LOC = "L13";
  X_IPAD \d[0]  (
    .PAD(d[0])
  );
  defparam \e[0] .LOC = "F12";
  X_OPAD \e[0]  (
    .PAD(e[0])
  );
  X_OBUF \e_obuf[0]  (
    .I(m5_0),
    .O(e[0])
  );
endmodule


`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

    wire GSR;
    wire GTS;
    wire PRLD;

    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (weak1, weak0) GSR = GSR_int;
    assign (weak1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule