people4_map.mrp

这是我自己写的4人表决器源码

Release 8.2.03i Map I.34
Xilinx Mapping Report File for Design 'people4'

Design Information
------------------
Command Line   : D:\Software\Xilinx ISE8.2\bin\nt\map.exe -ise
E:/Homework/ISE8.1 work/people4/people4.ise -intstyle ise -p xc3s500e-fg320-4
-cm area -pr b -k 4 -c 100 -o people4_map.ncd people4.ngd people4.pcf 
Target Device  : xc3s500e
Target Package : fg320
Target Speed   : -4
Mapper Version : spartan3e -- $Revision: 1.34.32.1 $
Mapped Date    : Fri Jan 19 11:25:02 2007

Design Summary
--------------
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of 4 input LUTs:               1 out of   9,312    1%
Logic Distribution:
  Number of occupied Slices:                            1 out of   4,656    1%
    Number of Slices containing only related logic:       1 out of       1  100%
    Number of Slices containing unrelated logic:          0 out of       1    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:           1 out of   9,312    1%
  Number of bonded IOBs:                5 out of     232    2%

Total equivalent gate count for design:  6
Additional JTAG gate count for IOBs:  240
Peak Memory Usage:  158 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.

Section 4 - Removed Logic Summary
---------------------------------

Section 5 - Removed Logic
-------------------------

Section 6 - IOB Properties
--------------------------

+-----------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | IOB Type         | Direction | IO Standard | Drive    | Slew | Reg (s)      | Resistor | IBUF/IFD  |
|                                    |                  |           |             | Strength | Rate |              |          | Delay     |
+-----------------------------------------------------------------------------------------------------------------------------------------+
| a[0]                               | IBUF             | INPUT     | LVCMOS25    |          |      |              |          | 0 / 0     |
| b[0]                               | IBUF             | INPUT     | LVCMOS25    |          |      |              |          | 0 / 0     |
| c[0]                               | IBUF             | INPUT     | LVCMOS25    |          |      |              |          | 0 / 0     |
| d[0]                               | IBUF             | INPUT     | LVCMOS25    |          |      |              |          | 0 / 0     |
| e[0]                               | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          | 0 / 0     |
+-----------------------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group and Partition Summary
--------------------------------------------

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Area Group Information
----------------------

  No area groups were found in this design.

----------------------

Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.

Section 11 - Timing Report
--------------------------
This design was not run using timing mode.

Section 12 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings