freq_change.vhdl

本代码介绍了使用VHDL开发FPGA的一般流程

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Freq_Change IS
	port(
		clk_in		:in STD_LOGIC;				--输入时钟脉冲
		clk_out1		:out STD_LOGIC;			--输出频率1HZ时钟脉冲
		clk_out10		:out STD_LOGIC;			--输出频率10HZ时钟脉冲
		clk_out100	:out STD_LOGIC;			--输出频率100HZ时钟脉冲
		CP10k		:out STD_LOGIC				--输出频率10KHZ时钟脉冲
	);
end Freq_Change;

architecture Behavioral of Freq_Change is
	component Free_Change	is
		Generic ( rate : integer:=10 );
	 	Port(
	 		clk_in 		:in STD_LOGIC;				--输入时钟脉冲
			clk_out		:out STD_LOGIC				--输出时钟脉冲
	 	);
    	end component;
	signal  out_temporary 	:std_logic_vector(0 to 4);
	signal  carry        	:std_logic;
begin
	U0:Free_Change generic map(rate=>3200) port map(clk_in=>clk_in,clk_out=>carry);

	out_temporary(0)<=carry;

	shift_counter:	for I in 0 to 3 generate
	 shift_change:	Free_Change port map (clk_in=>out_temporary(I),clk_out=>out_temporary(I+1));
	end generate;

	CP10k<=out_temporary(0);
	clk_out100<=out_temporary(2);
  	clk_out10<=out_temporary(3);
	clk_out1<=out_temporary(4);

end Behavioral;