gate_teat.vhd

来自「本代码介绍了使用VHDL开发FPGA的一般流程」· VHDL 代码 · 共 66 行

-- VHDL Test Bench Created from source file gate.vhd -- 18:03:26 12/13/2006
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY gate_test_vhd_tb IS
END gate_test_vhd_tb;

ARCHITECTURE behavior OF gate_test_vhd_tb IS 

	COMPONENT gate
	PORT(
		CLK : IN std_logic;
		gate0 : IN std_logic;          
		CP : OUT std_logic
		);
	END COMPONENT;

	SIGNAL CLK :  std_logic;
	SIGNAL gate0 :  std_logic;
	SIGNAL CP :  std_logic;

BEGIN

	uut: gate PORT MAP(
		CLK => CLK,
		gate0 => gate0,
		CP => CP
	);


-- *** Test Bench - User Defined Section ***
        tb : PROCESS
   BEGIN
      wait for 5 ns;
      clk<='1';
      wait for 15 ns;
	 clk<='0';
	 wait for 10 ns;
   END PROCESS;
   tb1 : PROCESS
   BEGIN
      wait for 10 ns;
      gate0<='1';
      wait for 90 ns;
	 gate0<='0';
	 wait for 80 ns;
	 gate0<='1';
      wait for 200 ns;
	 gate0<='0';
	 wait for 80 ns;

   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;