coregen.log

来自「本代码介绍了使用VHDL开发FPGA的一般流程」· LOG 代码 · 共 22 行

# Xilinx CORE Generator 6.2i
# User = Administrator
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in E:\lvbin\Freq_counter\coregen.log
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=E:\lvbin\Freq_counter
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=VHDL
# xilinxfamily=Virtex2
# outputoption=DesignFlow
# overwritefiles=Default
# simvendor=ModelSim
# expandedprojectpath=E:\lvbin\Freq_counter
SETPROJECT .
Set current Project to E:\lvbin\Freq_counter
SET BusFormat = BusFormatAngleBracketNotRipped
SETXIPCPORTHOST 1220
XIPCPJSENDCORES spartan2