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    Found 4-bit register for signal <BCD_2>.
    Found 4-bit register for signal <BCD_3>.
    Found 4-bit register for signal <BCD_4>.
    Found 4-bit register for signal <BCD_5>.
    Found 4-bit register for signal <BCD_6>.
    Summary:
	inferred  25 D-type flip-flop(s).
Unit <Data_Lock> synthesized.


Synthesizing Unit <Counter>.
    Related source file is E:/lvbin/Freq_counter/counter.vhdl.
Unit <Counter> synthesized.


Synthesizing Unit <GATE>.
    Related source file is E:/lvbin/Freq_counter/gate.vhdl.
Unit <GATE> synthesized.


Synthesizing Unit <Control_Unite>.
    Related source file is E:/lvbin/Freq_counter/control_unite.vhdl.
WARNING:Xst:1780 - Signal <LED> is never used or assigned.
    Found 1-bit register for signal <S1>.
    Found 1-bit register for signal <S2>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <Control_Unite> synthesized.


Synthesizing Unit <Freq_Change>.
    Related source file is E:/lvbin/Freq_counter/freq_change.vhdl.
Unit <Freq_Change> synthesized.


Synthesizing Unit <top>.
    Related source file is E:/lvbin/Freq_counter/Top.vhdl.
Unit <top> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 7
 16x7-bit ROM                      : 1
 16x4-bit ROM                      : 6
# Counters                         : 18
 12-bit up counter                 : 1
 4-bit up counter                  : 16
 3-bit up counter                  : 1
# Registers                        : 20
 1-bit register                    : 14
 4-bit register                    : 6
# Comparators                      : 11
 12-bit comparator less            : 1
 4-bit comparator less             : 10
# Multiplexers                     : 1
 4-bit 8-to-1 multiplexer          : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <top> ...

Optimizing unit <Control_Unite> ...

Optimizing unit <Data_Lock> ...

Optimizing unit <BCD2SEG_Display> ...
Loading device for application Xst from file 'v100.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 11.
FlipFlop U5_S_0 has been replicated 1 time(s)
FlipFlop U5_S_1 has been replicated 1 time(s)
FlipFlop U5_S_2 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100pq208-6 

 Number of Slices:                     137  out of   1200    11%  
 Number of Slice Flip Flops:           120  out of   2400     5%  
 Number of 4 input LUTs:               198  out of   2400     8%  
 Number of bonded IOBs:                 49  out of    144    34%  
 Number of GCLKs:                        2  out of      4    50%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
U1_S1:Q                            | NONE                   | 25    |
U0_shift_change2_clk_out:Q         | NONE                   | 5     |
U0_shift_change1_clk_out:Q         | NONE                   | 5     |
CLK_Basic                          | BUFGP                  | 13    |
U0_U0_clk_out:Q                    | NONE                   | 11    |
U0_shift_change0_clk_out:Q         | NONE                   | 5     |
U3_U4_Fdiv_clk_out:Q               | NONE                   | 9     |
CP(U2_CP1:O)                       | NONE(*)(U3_U0_Fdiv_clk_out)| 9     |
U3_U3_Fdiv_clk_out:Q               | NONE                   | 9     |
U3_U2_Fdiv_clk_out:Q               | NONE                   | 9     |
U3_U1_Fdiv_clk_out:Q               | NONE                   | 9     |
U3_U0_Fdiv_clk_out:Q               | NONE                   | 9     |
U1_clk(U1_clk36:O)                 | NONE(*)(U1_S2)         | 2     |
-----------------------------------+------------------------+-------+
(*) These 2 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 6.383ns (Maximum Frequency: 156.666MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 16.896ns
   Maximum combinational path delay: 8.594ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\lvbin\freq_counter/_ngo -uc top.ucf
-p xc2s100-pq208-6 top.ngc top.ngd 

Reading NGO file "E:/lvbin/Freq_counter/top.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "top.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:477 - clock net 'CLK_BUFGP' has non-clock connections. These
   problematic connections include:
     pin I0 on block U2_CP1 with type LUT2
WARNING:NgdBuild:478 - clock net 'CLK_BUFGP' drives no clock pins

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   2

Total memory usage is 40160 kilobytes

Writing NGD file "top.ngd" ...

Writing NGDBUILD log file "top.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s100pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    3
Logic Utilization:
  Number of Slice Flip Flops:       119 out of  2,400    4%
  Number of 4 input LUTs:           137 out of  2,400    5%
Logic Distribution:
    Number of occupied Slices:                         133 out of  1,200   11%
    Number of Slices containing only related logic:    133 out of    133  100%
    Number of Slices containing unrelated logic:         0 out of    133    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          196 out of  2,400    8%
      Number used as logic:                       137
      Number used as a route-thru:                 59
   Number of bonded IOBs:            49 out of    140   35%
      IOB Flip Flops:                               1
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%

Total equivalent gate count for design:  2,175
Additional JTAG gate count for IOBs:  2,448
Peak Memory Usage:  61 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "top_map.mrp" for details.
Completed process "Map".

Mapping Module top . . .
MAP command line:
map -intstyle ise -p xc2s100-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o top_map.ncd top.ngd top.pcf
Mapping Module top: DONE



Started process "Place & Route".





Constraints file: top.pcf

Loading device database for application Par from file "top_map.ncd".
   "top" is an NCD, version 2.38, device xc2s100, package pq208, speed -6
Loading device for application Par from file 'v100.nph' in environment
C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         2 out of 4      50%
   Number of External IOBs            49 out of 140    35%
      Number of LOCed External IOBs    0 out of 49      0%

   Number of SLICEs                  133 out of 1200   11%

   Number of GCLKs                     2 out of 4      50%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989ae6) REAL time: 2 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.8
.....
Phase 5.8 (Checksum:a0edd9) REAL time: 2 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 2 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs 

Writing design to file top.ncd.

Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 775 unrouted;       REAL time: 3 secs 

Phase 2: 693 unrouted;       REAL time: 19 secs 

Phase 3: 161 unrouted;       REAL time: 21 secs 

Phase 4: 0 unrouted;       REAL time: 21 secs 

Total REAL time to Router completion: 22 secs 
Total CPU time to Router completion: 18 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|   CLK_Basic_BUFGP          |  Global  |    7   |  0.002     |  0.481      |
+----------------------------+----------+--------+------------+-------------+
|U0_shift_change0_clk_out    |Low-Skew  |    3   |  0.326     |  4.782      |
+----------------------------+----------+--------+------------+-------------+
|             U1_S1          |   Local  |   34   |  1.368     |  3.381      |
+----------------------------+----------+--------+------------+-------------+
|U3_U2_Fdiv_clk_out          |   Local  |    5   |  1.744     |  2.808      |
+----------------------------+----------+--------+------------+-------------+
|U3_U3_Fdiv_clk_out          |   Local  |    5   |  1.727     |  3.034      |
+----------------------------+----------+--------+------------+-------------+
|                CP          |   Local  |    5   |  0.116     |  2.883      |
+----------------------------+----------+--------+------------+-------------+
|U3_U4_Fdiv_clk_out          |   Local  |    5   |  0.048