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Unit <Free_Change0> synthesized.


Synthesizing Unit <Free_Change>.
    Related source file is E:/lvbin/Freq_counter/free_change.vhdl.
    Found 1-bit register for signal <clk_out>.
    Found 12-bit comparator less for signal <$n0002> created at line 27.
    Found 12-bit up counter for signal <count>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <Free_Change> synthesized.


Synthesizing Unit <BCD2SEG_Display>.
    Related source file is E:/lvbin/Freq_counter/bcd2seg_display.vhdl.
    Found 16x7-bit ROM for signal <SEG>.
    Found 4-bit 8-to-1 multiplexer for signal <DB>.
    Found 3-bit up counter for signal <S>.
    Summary:
	inferred   1 ROM(s).
	inferred   1 Counter(s).
	inferred   4 Multiplexer(s).
Unit <BCD2SEG_Display> synthesized.


Synthesizing Unit <Data_Lock>.
    Related source file is E:/lvbin/Freq_counter/data_lock.vhdl.
    Found 1-bit register for signal <OVER>.
    Found 4-bit register for signal <BCD_1>.
    Found 4-bit register for signal <BCD_2>.
    Found 4-bit register for signal <BCD_3>.
    Found 4-bit register for signal <BCD_4>.
    Found 4-bit register for signal <BCD_5>.
    Found 4-bit register for signal <BCD_6>.
    Summary:
	inferred  25 D-type flip-flop(s).
Unit <Data_Lock> synthesized.


Synthesizing Unit <Counter>.
    Related source file is E:/lvbin/Freq_counter/counter.vhdl.
Unit <Counter> synthesized.


Synthesizing Unit <GATE>.
    Related source file is E:/lvbin/Freq_counter/gate.vhdl.
Unit <GATE> synthesized.


Synthesizing Unit <Control_Unite>.
    Related source file is E:/lvbin/Freq_counter/control_unite.vhdl.
WARNING:Xst:1780 - Signal <LED> is never used or assigned.
    Found 1-bit register for signal <S1>.
    Found 1-bit register for signal <S2>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <Control_Unite> synthesized.


Synthesizing Unit <Freq_Change>.
    Related source file is E:/lvbin/Freq_counter/freq_change.vhdl.
Unit <Freq_Change> synthesized.


Synthesizing Unit <top>.
    Related source file is E:/lvbin/Freq_counter/Top.vhdl.
Unit <top> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 7
 16x7-bit ROM                      : 1
 16x4-bit ROM                      : 6
# Counters                         : 18
 12-bit up counter                 : 1
 4-bit up counter                  : 16
 3-bit up counter                  : 1
# Registers                        : 20
 1-bit register                    : 14
 4-bit register                    : 6
# Comparators                      : 11
 12-bit comparator less            : 1
 4-bit comparator less             : 10
# Multiplexers                     : 1
 4-bit 8-to-1 multiplexer          : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <top> ...

Optimizing unit <Control_Unite> ...

Optimizing unit <Data_Lock> ...

Optimizing unit <BCD2SEG_Display> ...
Loading device for application Xst from file 'v100.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 11.
FlipFlop U5_S_0 has been replicated 1 time(s)
FlipFlop U5_S_1 has been replicated 1 time(s)
FlipFlop U5_S_2 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100pq208-6 

 Number of Slices:                     137  out of   1200    11%  
 Number of Slice Flip Flops:           120  out of   2400     5%  
 Number of 4 input LUTs:               198  out of   2400     8%  
 Number of bonded IOBs:                 49  out of    144    34%  
 Number of GCLKs:                        2  out of      4    50%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
U1_S1:Q                            | NONE                   | 25    |
U0_shift_change2_clk_out:Q         | NONE                   | 5     |
U0_shift_change1_clk_out:Q         | NONE                   | 5     |
CLK_Basic                          | BUFGP                  | 13    |
U0_U0_clk_out:Q                    | NONE                   | 11    |
U0_shift_change0_clk_out:Q         | NONE                   | 5     |
U3_U4_Fdiv_clk_out:Q               | NONE                   | 9     |
CP(U2_CP1:O)                       | NONE(*)(U3_U0_Fdiv_clk_out)| 9     |
U3_U3_Fdiv_clk_out:Q               | NONE                   | 9     |
U3_U2_Fdiv_clk_out:Q               | NONE                   | 9     |
U3_U1_Fdiv_clk_out:Q               | NONE                   | 9     |
U3_U0_Fdiv_clk_out:Q               | NONE                   | 9     |
U1_clk(U1_clk36:O)                 | NONE(*)(U1_S2)         | 2     |
-----------------------------------+------------------------+-------+
(*) These 2 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 6.383ns (Maximum Frequency: 156.666MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 16.896ns
   Maximum combinational path delay: 8.594ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\lvbin\freq_counter/_ngo -uc top.ucf
-p xc2s100-pq208-6 top.ngc top.ngd 

Reading NGO file "E:/lvbin/Freq_counter/top.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "top.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:477 - clock net 'CLK_BUFGP' has non-clock connections. These
   problematic connections include:
     pin I0 on block U2_CP1 with type LUT2
WARNING:NgdBuild:478 - clock net 'CLK_BUFGP' drives no clock pins

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   2

Total memory usage is 40160 kilobytes

Writing NGD file "top.ngd" ...

Writing NGDBUILD log file "top.bld"...

NGDBUILD done.
Completed process "Translate".



Project Navigator Auto-Make Log File
-------------------------------------



Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file E:/lvbin/Freq_counter/free_change.vhdl in Library work.
Architecture behavioral of Entity free_change is up to date.
Compiling vhdl file E:/lvbin/Freq_counter/counter10.vhdl in Library work.
Architecture behavioral of Entity counter10 is up to date.
Compiling vhdl file E:/lvbin/Freq_counter/freq_change.vhdl in Library work.
Architecture behavioral of Entity freq_change is up to date.
Compiling vhdl file E:/lvbin/Freq_counter/control_unite.vhdl in Library work.
Architecture behavioral of Entity control_unite is up to date.
Compiling vhdl file E:/lvbin/Freq_counter/gate.vhdl in Library work.
Architecture behavioral of Entity gate is up to date.
Compiling vhdl file E:/lvbin/Freq_counter/counter.vhdl in Library work.
Architecture behavioral of Entity counter is up to date.
Compiling vhdl file E:/lvbin/Freq_counter/data_lock.vhdl in Library work.
Architecture behavioral of Entity data_lock is up to date.
Compiling vhdl file E:/lvbin/Freq_counter/bcd2seg_display.vhdl in Library work.
Architecture behavioral of Entity bcd2seg_display is up to date.
Compiling vhdl file E:/lvbin/Freq_counter/Top.vhdl in Library work.
Architecture behavior of Entity top is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top> (Architecture <behavior>).
    Set property "buffer_type = bufGP" for signal <CLK> in unit <top>.
Entity <top> analyzed. Unit <top> generated.

Analyzing Entity <Freq_Change> (Architecture <behavioral>).
    Set property "buffer_type = ibuf" for signal <clk_in> in unit <Free_Change>.
    Set property "buffer_type = ibuf" for signal <clk_in> in unit <Free_Change0_>.
    Set property "buffer_type = ibuf" for signal <clk_in> in unit <Free_Change0_> (previous value was "ibuf").
    Set property "buffer_type = ibuf" for signal <clk_in> in unit <Free_Change0_> (previous value was "ibuf").
    Set property "buffer_type = ibuf" for signal <clk_in> in unit <Free_Change0_> (previous value was "ibuf").
Entity <Freq_Change> analyzed. Unit <Freq_Change> generated.

Analyzing generic Entity <Free_Change> (Architecture <behavioral>).
	rate = 3200
    Set property "buffer_type = ibuf" for signal <clk_in> in unit <Free_Change> (previous value was "ibuf").
Entity <Free_Change> analyzed. Unit <Free_Change> generated.

Analyzing generic Entity <Free_Change> (Architecture <behavioral>).
	rate = 10
    Set property "buffer_type = ibuf" for signal <clk_in> in unit <Free_Change0_> (previous value was "ibuf").
Entity <Free_Change> analyzed. Unit <Free_Change0> generated.

Analyzing Entity <Control_Unite> (Architecture <behavioral>).
Entity <Control_Unite> analyzed. Unit <Control_Unite> generated.

Analyzing Entity <GATE> (Architecture <behavioral>).
Entity <GATE> analyzed. Unit <GATE> generated.

Analyzing Entity <Counter> (Architecture <behavioral>).
Entity <Counter> analyzed. Unit <Counter> generated.

Analyzing Entity <counter10> (Architecture <behavioral>).
    Set property "buffer_type = ibuf" for signal <clk_in> in unit <Free_Change0_> (previous value was "ibuf").
Entity <counter10> analyzed. Unit <counter10> generated.

Analyzing Entity <Data_Lock> (Architecture <behavioral>).
Entity <Data_Lock> analyzed. Unit <Data_Lock> generated.

Analyzing Entity <BCD2SEG_Display> (Architecture <behavioral>).
Entity <BCD2SEG_Display> analyzed. Unit <BCD2SEG_Display> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <counter10>.
    Related source file is E:/lvbin/Freq_counter/counter10.vhdl.
    Found 16x4-bit ROM for signal <count_BCD_out>.
    Found 4-bit up counter for signal <Q>.
    Summary:
	inferred   1 ROM(s).
	inferred   1 Counter(s).
Unit <counter10> synthesized.


Synthesizing Unit <Free_Change0>.
    Related source file is E:/lvbin/Freq_counter/free_change.vhdl.
    Found 1-bit register for signal <clk_out>.
    Found 4-bit comparator less for signal <$n0002> created at line 27.
    Found 4-bit up counter for signal <count>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <Free_Change0> synthesized.


Synthesizing Unit <Free_Change>.
    Related source file is E:/lvbin/Freq_counter/free_change.vhdl.
    Found 1-bit register for signal <clk_out>.
    Found 12-bit comparator less for signal <$n0002> created at line 27.
    Found 12-bit up counter for signal <count>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <Free_Change> synthesized.


Synthesizing Unit <BCD2SEG_Display>.
    Related source file is E:/lvbin/Freq_counter/bcd2seg_display.vhdl.
    Found 16x7-bit ROM for signal <SEG>.
    Found 4-bit 8-to-1 multiplexer for signal <DB>.
    Found 3-bit up counter for signal <S>.
    Summary:
	inferred   1 ROM(s).
	inferred   1 Counter(s).
	inferred   4 Multiplexer(s).
Unit <BCD2SEG_Display> synthesized.


Synthesizing Unit <Data_Lock>.
    Related source file is E:/lvbin/Freq_counter/data_lock.vhdl.
    Found 1-bit register for signal <OVER>.
    Found 4-bit register for signal <BCD_1>.