freq_counter.gfl

来自「本代码介绍了使用VHDL开发FPGA的一般流程」· GFL 代码 · 共 185 行

# XST (Creating Lso File) : 
top.lso
# xst flow : RunXST
top.syr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
top.ngc
top.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
e:\lvbin\freq_counter/_ngo
top.ngd
top_ngdbuild.nav
top.bld
top.ucf.untf
top.cmd_log
# Implementation : Map
top_map.ncd
top.ngm
top.pcf
top.nc1
top.mrp
top_map.mrp
top.mdf
__projnav/map.log
top.cmd_log
MAP_NO_GUIDE_FILE_CPF "top"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
top.twr
top.twx
top.tsi
top.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
top.ncd
top.par
top.pad
top_pad.txt
top_pad.csv
top.pad_txt
top.dly
reportgen.log
top.xpi
top.grf
top.itr
top_last_par.ncd
__projnav/par.log
top.placed_ncd_tracker
top.routed_ncd_tracker
top.cmd_log
PAR_NO_GUIDE_FILE_CPF "top"
# Generate Programming File
__projnav/top_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
top.ut
# Generate Programming File
top.bgn
top.rbt
top.ll
top.msk
top.drc
top.nky
top.bit
top.bin
top.isc
top.cmd_log
# ModelSim : Simulate Behavioral VHDL Model
top_top_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
gate_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# XST (Creating Lso File) : 
free_change.lso
# xst flow : RunXST
free_change.syr
free_change.prj
free_change.sprj
free_change.ana
free_change.stx
free_change.cmd_log
free_change.ngr
# View RTL Schematic
free_change.ngr
# XST (Creating Lso File) : 
control_unite.lso
# xst flow : RunXST
control_unite.syr
control_unite.prj
control_unite.sprj
control_unite.ana
control_unite.stx
control_unite.cmd_log
control_unite.ngr
# ModelSim : Simulate Behavioral VHDL Model
control_unite_control_unite_test_vhd_tb.fdo
# View RTL Schematic
control_unite.ngr
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
counter_counter_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# XST (Creating Lso File) : 
counter.lso
# xst flow : RunXST
counter.syr
counter.prj
counter.sprj
counter.ana
counter.stx
counter.cmd_log
counter.ngr
# XST (Creating Lso File) : 
data_lock.lso
# xst flow : RunXST
data_lock.syr
data_lock.prj
data_lock.sprj
data_lock.ana
data_lock.stx
data_lock.cmd_log
data_lock.ngr
# View RTL Schematic
data_lock.ngr
# ModelSim : Simulate Behavioral VHDL Model
data_lock_data_lock_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# XST (Creating Lso File) : 
freq_change.lso
# xst flow : RunXST
freq_change.syr
freq_change.prj
freq_change.sprj
freq_change.ana
freq_change.stx
freq_change.cmd_log
free_change.ngr
freq_change.ngr
# View RTL Schematic
freq_change.ngr
# View RTL Schematic
counter.ngr
# XST (Creating Lso File) : 
counter10.lso
# xst flow : RunXST
counter10.syr
counter10.prj
counter10.sprj
counter10.ana
counter10.stx
counter10.cmd_log
counter10.ngr
# ModelSim : Simulate Behavioral VHDL Model
bcd2seg_display_bcd2seg_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# XST (Creating Lso File) : 
bcd2seg_display.lso
# xst flow : RunXST
bcd2seg_display.syr
bcd2seg_display.prj
bcd2seg_display.sprj
bcd2seg_display.ana
bcd2seg_display.stx
bcd2seg_display.cmd_log
bcd2seg_display.ngr
# View RTL Schematic
bcd2seg_display.ngr
# View RTL Schematic
counter10.ngr
# View RTL Schematic
top.ngr