top.par

来自「本代码介绍了使用VHDL开发FPGA的一般流程」· PAR 代码 · 共 204 行

Release 6.2i Par G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

UESTC::  Mon Dec 18 22:40:37 2006


C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 top_map.ncd top.ncd
top.pcf 


Constraints file: top.pcf

Loading device database for application Par from file "top_map.ncd".
   "top" is an NCD, version 2.38, device xc2s100, package pq208, speed -6
Loading device for application Par from file 'v100.nph' in environment
C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolved that IOB <LED2_SEG<0>> must be placed at site P90.
Resolved that IOB <LED2_SEG<1>> must be placed at site P94.
Resolved that IOB <LED2_SEG<2>> must be placed at site P84.
Resolved that IOB <LED2_SEG<3>> must be placed at site P86.
Resolved that IOB <LED6_SEG<0>> must be placed at site P49.
Resolved that IOB <LED2_SEG<4>> must be placed at site P88.
Resolved that IOB <LED6_SEG<1>> must be placed at site P57.
Resolved that IOB <LED2_SEG<5>> must be placed at site P96.
Resolved that IOB <LED6_SEG<2>> must be placed at site P46.
Resolved that IOB <LED2_SEG<6>> must be placed at site P95.
Resolved that IOB <LED6_SEG<3>> must be placed at site P47.
Resolved that IOB <LED6_SEG<4>> must be placed at site P48.
Resolved that IOB <LED6_SEG<5>> must be placed at site P61.
Resolved that IOB <LED6_SEG<6>> must be placed at site P59.
Resolved that IOB <LED_point<0>> must be placed at site P120.
Resolved that IOB <LED_point<1>> must be placed at site P115.
Resolved that IOB <LED_point<2>> must be placed at site P113.
Resolved that IOB <LED3_SEG<0>> must be placed at site P74.
Resolved that IOB <LED3_SEG<1>> must be placed at site P75.
Resolved that IOB <LED3_SEG<2>> must be placed at site P70.
Resolved that IOB <Switch<0>> must be placed at site P5.
Resolved that IOB <LED3_SEG<3>> must be placed at site P71.
Resolved that IOB <Switch<1>> must be placed at site P4.
Resolved that IOB <LED3_SEG<4>> must be placed at site P73.
Resolved that IOB <Switch<2>> must be placed at site P3.
Resolved that IOB <LED3_SEG<5>> must be placed at site P82.
Resolved that IOB <LED3_SEG<6>> must be placed at site P81.
Resolved that GCLKIOB <CLK_Basic> must be placed at site P182.
Resolved that IOB <LED4_SEG<0>> must be placed at site P62.
Resolved that IOB <LED4_SEG<1>> must be placed at site P63.
Resolved that IOB <LED4_SEG<2>> must be placed at site P69.
Resolved that IOB <LED4_SEG<3>> must be placed at site P58.
Resolved that IOB <LED4_SEG<4>> must be placed at site P60.
Resolved that IOB <LED4_SEG<5>> must be placed at site P68.
Resolved that IOB <LED4_SEG<6>> must be placed at site P67.
Resolved that IOB <RST> must be placed at site P193.
Resolved that IOB <LED1_SEG<0>> must be placed at site P109.
Resolved that IOB <LED1_SEG<1>> must be placed at site P110.
Resolved that IOB <LED1_SEG<2>> must be placed at site P101.
Resolved that IOB <LED1_SEG<3>> must be placed at site P102.
Resolved that IOB <LED5_SEG<0>> must be placed at site P97.
Resolved that IOB <OVER> must be placed at site P134.
Resolved that IOB <LED1_SEG<4>> must be placed at site P108.
Resolved that IOB <LED5_SEG<1>> must be placed at site P89.
Resolved that IOB <LED1_SEG<5>> must be placed at site P112.
Resolved that IOB <LED5_SEG<2>> must be placed at site P100.
Resolved that IOB <LED1_SEG<6>> must be placed at site P111.
Resolved that IOB <LED5_SEG<3>> must be placed at site P99.
Resolved that GCLKIOB <CLK> must be placed at site P80.
Resolved that IOB <LED5_SEG<4>> must be placed at site P98.
Resolved that IOB <LED5_SEG<5>> must be placed at site P83.
Resolved that IOB <LED_gate> must be placed at site P132.
Resolved that IOB <LED5_SEG<6>> must be placed at site P87.


Device utilization summary:

   Number of External GCLKIOBs         2 out of 4      50%
   Number of External IOBs            51 out of 140    36%
      Number of LOCed External IOBs   51 out of 51    100%

   Number of SLICEs                  127 out of 1200   10%

   Number of GCLKs                     2 out of 4      50%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989af4) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.....
Phase 5.8 (Checksum:a13c8f) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file top.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 817 unrouted;       REAL time: 0 secs 

Phase 2: 752 unrouted;       REAL time: 7 secs 

Phase 3: 185 unrouted;       REAL time: 7 secs 

Phase 4: 0 unrouted;       REAL time: 8 secs 

Total REAL time to Router completion: 8 secs 
Total CPU time to Router completion: 7 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|   CLK_Basic_BUFGP          |  Global  |    8   |  0.069     |  0.499      |
+----------------------------+----------+--------+------------+-------------+
|U0_shift_change1_clk_out    |Low-Skew  |    5   |  0.026     |  4.608      |
+----------------------------+----------+--------+------------+-------------+
|     U0_U0_clk_out          |   Local  |    7   |  0.240     |  3.027      |
+----------------------------+----------+--------+------------+-------------+
|             U3_S1          |   Local  |    3   |  0.244     |  1.251      |
+----------------------------+----------+--------+------------+-------------+
|             U3_S2          |   Local  |    3   |  0.060     |  2.795      |
+----------------------------+----------+--------+------------+-------------+
|             U3_S3          |   Local  |    3   |  0.029     |  2.673      |
+----------------------------+----------+--------+------------+-------------+
|             U3_S4          |   Local  |    3   |  0.002     |  2.907      |
+----------------------------+----------+--------+------------+-------------+
|             U3_S5          |   Local  |    3   |  0.069     |  2.717      |
+----------------------------+----------+--------+------------+-------------+
|          U3_carry          |   Local  |    1   |  0.000     |  0.573      |
+----------------------------+----------+--------+------------+-------------+
|U0_shift_change0_clk_out    |   Local  |    4   |  0.042     |  2.948      |
+----------------------------+----------+--------+------------+-------------+
|U0_shift_change2_clk_out    |   Local  |    5   |  0.108     |  3.065      |
+----------------------------+----------+--------+------------+-------------+
|              LOAD          |   Local  |   14   |  1.533     |  2.751      |
+----------------------------+----------+--------+------------+-------------+
|            U1_clk          |   Local  |    3   |  1.626     |  4.345      |
+----------------------------+----------+--------+------------+-------------+
|                CP          |   Local  |    3   |  0.000     |  2.596      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 212


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.420
   The MAXIMUM PIN DELAY IS:                               4.608
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   3.504

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         296         336         168          11           6           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 8 secs 
Total CPU time to PAR completion: 7 secs 

Peak Memory Usage:  55 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file top.ncd.


PAR done.