counter_test.vhd

来自「本代码介绍了使用VHDL开发FPGA的一般流程」· VHDL 代码 · 共 78 行

-- VHDL Test Bench Created from source file counter.vhd -- 20:39:04 12/13/2006
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY counter_counter_test_vhd_tb IS
END counter_counter_test_vhd_tb;

ARCHITECTURE behavior OF counter_counter_test_vhd_tb IS 

	COMPONENT counter
	PORT(
		Reset : IN std_logic;
		clk : IN std_logic;          
		OVER : OUT std_logic;
		F : OUT std_logic_vector(3 downto 0);
		E : OUT std_logic_vector(3 downto 0);
		D : OUT std_logic_vector(3 downto 0);
		C : OUT std_logic_vector(3 downto 0);
		B : OUT std_logic_vector(3 downto 0);
		A : OUT std_logic_vector(3 downto 0)
		);
	END COMPONENT;

	SIGNAL Reset :  std_logic;
	SIGNAL clk :  std_logic;
	SIGNAL OVER :  std_logic;
	SIGNAL F :  std_logic_vector(3 downto 0);
	SIGNAL E :  std_logic_vector(3 downto 0);
	SIGNAL D :  std_logic_vector(3 downto 0);
	SIGNAL C :  std_logic_vector(3 downto 0);
	SIGNAL B :  std_logic_vector(3 downto 0);
	SIGNAL A :  std_logic_vector(3 downto 0);

BEGIN

	uut: counter PORT MAP(
		Reset => Reset,
		clk => clk,
		OVER => OVER,
		F => F,
		E => E,
		D => D,
		C => C,
		B => B,
		A => A
	);


-- *** Test Bench - User Defined Section ***
   tb1 : PROCESS
   BEGIN
      clk <= '1';
      wait for 10 ns;
      clk <= '0';
      wait for 10 ns;
   END PROCESS;
   tb2 : PROCESS
   BEGIN
      Reset <= '0';
      wait for 5 ns;
      Reset <= '1';
      wait for 1 sec; 
   END PROCESS;
   
-- *** End Test Bench - User Defined Section ***

END;