bcd2seg_test.vhd

来自「本代码介绍了使用VHDL开发FPGA的一般流程」· VHDL 代码 · 共 104 行

-- VHDL Test Bench Created from source file bcd2seg_display.vhd -- 17:01:26 12/15/2006
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY bcd2seg_display_bcd2seg_test_vhd_tb IS
END bcd2seg_display_bcd2seg_test_vhd_tb;

ARCHITECTURE behavior OF bcd2seg_display_bcd2seg_test_vhd_tb IS 

	COMPONENT bcd2seg_display
	PORT(
		BCD_6 : IN std_logic_vector(3 downto 0);
		BCD_5 : IN std_logic_vector(3 downto 0);
		BCD_4 : IN std_logic_vector(3 downto 0);
		BCD_3 : IN std_logic_vector(3 downto 0);
		BCD_2 : IN std_logic_vector(3 downto 0);
		BCD_1 : IN std_logic_vector(3 downto 0);
		CP : IN std_logic;
		OVER_flow : IN std_logic;          
		SEG_6 : OUT std_logic_vector(6 downto 0);
		SEG_5 : OUT std_logic_vector(6 downto 0);
		SEG_4 : OUT std_logic_vector(6 downto 0);
		SEG_3 : OUT std_logic_vector(6 downto 0);
		SEG_2 : OUT std_logic_vector(6 downto 0);
		SEG_1 : OUT std_logic_vector(6 downto 0)
		);
	END COMPONENT;

	SIGNAL BCD_6 :  std_logic_vector(3 downto 0);
	SIGNAL BCD_5 :  std_logic_vector(3 downto 0);
	SIGNAL BCD_4 :  std_logic_vector(3 downto 0);
	SIGNAL BCD_3 :  std_logic_vector(3 downto 0);
	SIGNAL BCD_2 :  std_logic_vector(3 downto 0);
	SIGNAL BCD_1 :  std_logic_vector(3 downto 0);
	SIGNAL CP :  std_logic;
	SIGNAL OVER_flow :  std_logic;
	SIGNAL SEG_6 :  std_logic_vector(6 downto 0);
	SIGNAL SEG_5 :  std_logic_vector(6 downto 0);
	SIGNAL SEG_4 :  std_logic_vector(6 downto 0);
	SIGNAL SEG_3 :  std_logic_vector(6 downto 0);
	SIGNAL SEG_2 :  std_logic_vector(6 downto 0);
	SIGNAL SEG_1 :  std_logic_vector(6 downto 0);

BEGIN

	uut: bcd2seg_display PORT MAP(
		BCD_6 => BCD_6,
		BCD_5 => BCD_5,
		BCD_4 => BCD_4,
		BCD_3 => BCD_3,
		BCD_2 => BCD_2,
		BCD_1 => BCD_1,
		CP => CP,
		OVER_flow => OVER_flow,
		SEG_6 => SEG_6,
		SEG_5 => SEG_5,
		SEG_4 => SEG_4,
		SEG_3 => SEG_3,
		SEG_2 => SEG_2,
		SEG_1 => SEG_1
	);


-- *** Test Bench - User Defined Section ***
   tb1 : PROCESS
   BEGIN
      CP<='0';
	 wait for 10 ns;
	 CP<='1';
	 wait for 10 ns;
   END PROCESS;

   tb2 : PROCESS
   BEGIN
   BCD_6<="0000";
   BCD_5<="1000";
   BCD_4<="0110";
   BCD_3<="1001";
   BCD_2<="0101";
   BCD_1<="1000";
   wait for 1 sec ;
   END PROCESS;

   tb3 : PROCESS
   BEGIN
   	 OVER_flow<='0';
	 wait for 100 ns;
      OVER_flow<='1';
	 wait for 1 sec;
   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;