top_test.vhd

本代码介绍了使用VHDL开发FPGA的一般流程

-- VHDL Test Bench Created from source file top.vhd -- 09:47:39 12/18/2006
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY top_top_test_vhd_tb IS
END top_top_test_vhd_tb;

ARCHITECTURE behavior OF top_top_test_vhd_tb IS 

	COMPONENT top
	PORT(
		CLK_Basic : IN std_logic;
		CLK : IN std_logic;
		RST : IN std_logic;
		Switch : IN std_logic_vector(2 downto 0);          
		LED_point : OUT std_logic_vector(0 to 2);
		LED6_SEG : OUT std_logic_vector(6 downto 0);
		LED5_SEG : OUT std_logic_vector(6 downto 0);
		LED4_SEG : OUT std_logic_vector(6 downto 0);
		LED3_SEG : OUT std_logic_vector(6 downto 0);
		LED2_SEG : OUT std_logic_vector(6 downto 0);
		LED1_SEG : OUT std_logic_vector(6 downto 0);
		OVER : OUT std_logic;
		LED_gate : OUT std_logic
		);
	END COMPONENT;

	SIGNAL CLK_Basic :  std_logic;
	SIGNAL CLK :  std_logic;
	SIGNAL RST :  std_logic;
	SIGNAL Switch :  std_logic_vector(2 downto 0);
	SIGNAL LED_point :  std_logic_vector(0 to 2);
	SIGNAL LED6_SEG :  std_logic_vector(6 downto 0);
	SIGNAL LED5_SEG :  std_logic_vector(6 downto 0);
	SIGNAL LED4_SEG :  std_logic_vector(6 downto 0);
	SIGNAL LED3_SEG :  std_logic_vector(6 downto 0);
	SIGNAL LED2_SEG :  std_logic_vector(6 downto 0);
	SIGNAL LED1_SEG :  std_logic_vector(6 downto 0);
	SIGNAL OVER :  std_logic;
	SIGNAL LED_gate :  std_logic;

BEGIN

	uut: top PORT MAP(
		CLK_Basic => CLK_Basic,
		CLK => CLK,
		RST => RST,
		Switch => Switch,
		LED_point => LED_point,
		LED6_SEG => LED6_SEG,
		LED5_SEG => LED5_SEG,
		LED4_SEG => LED4_SEG,
		LED3_SEG => LED3_SEG,
		LED2_SEG => LED2_SEG,
		LED1_SEG => LED1_SEG,
		OVER => OVER,
		LED_gate => LED_gate
	);


-- *** Test Bench - User Defined Section ***
   tb1 : PROCESS
   BEGIN
   CLK_Basic<='0';
   wait for 15.625 ns;
   CLK_Basic<='1';
   wait for 15.625 ns;
   END PROCESS;
   tb2 : PROCESS
   BEGIN
   CLK<='0';
   wait for 0.02 ms;
   CLK<='1';
   wait for 0.02 ms;   		
   END PROCESS;
   tb3 : PROCESS
   BEGIN
   RST<='1';
   wait for 3 sec;  		
   END PROCESS;
   tb4 : PROCESS
   BEGIN
   Switch<="011";
   wait for 2 sec;  		
   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;