📄 top.mrp
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Release 6.2i Map G.28Xilinx Mapping Report File for Design 'top'Design Information------------------Command Line : C:/Xilinx/bin/nt/map.exe -intstyle ise -p xc2s100-pq208-6 -cm
area -pr b -k 4 -c 100 -tx off -o top_map.ncd top.ngd top.pcf Target Device : x2s100Target Package : pq208Target Speed : -6Mapper Version : spartan2 -- $Revision: 1.16.8.1 $Mapped Date : Mon Dec 18 22:40:34 2006Design Summary--------------Number of errors: 0Number of warnings: 10Logic Utilization: Total Number Slice Registers: 91 out of 2,400 3% Number used as Flip Flops: 66 Number used as Latches: 25 Number of 4 input LUTs: 173 out of 2,400 7%Logic Distribution: Number of occupied Slices: 127 out of 1,200 10% Number of Slices containing only related logic: 127 out of 127 100% Number of Slices containing unrelated logic: 0 out of 127 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs: 219 out of 2,400 9% Number used as logic: 173 Number used as a route-thru: 46 Number of bonded IOBs: 51 out of 140 36% IOB Flip Flops: 1 IOB Latches: 1 Number of GCLKs: 2 out of 4 50% Number of GCLKIOBs: 2 out of 4 50%Total equivalent gate count for design: 1,989Additional JTAG gate count for IOBs: 2,544Peak Memory Usage: 61 MBNOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 13 - Additional Device Resource CountsSection 1 - Errors------------------Section 2 - Warnings--------------------WARNING:LIT:178 - Clock buffer BUFG symbol "CLK_BUFGP/BUFG" (output
signal=CLK_BUFGP) does not drive clock loads. Driving only non-clock loads
with a clock buffer will cause ALL of the dedicated clock routing resources
for this buffer to be wasted. The non-clock loads are: Pin I0 of U2_CP1WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net U3_S1 is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net U3_S2 is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net U3_S3 is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net U3_S4 is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net U3_S5 is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net U3_carry is sourced
by a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net LOAD is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net U1_clk is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net CP is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.Section 3 - Informational-------------------------INFO:LIT:95 - All of the external outputs in this design are using slew rate
limited output drivers. The delay on speed critical outputs can be
dramatically reduced by designating them as fast outputs in the schematic.INFO:MapLib:562 - No environment variables are currently set.Section 4 - Removed Logic Summary--------------------------------- 2 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE BLOCKGND XST_GNDVCC XST_VCCTo enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Strength | Rate | | | Delay |+------------------------------------------------------------------------------------------------------------------------+| CLK | GCLKIOB | INPUT | LVTTL | | | | | || CLK_Basic | GCLKIOB | INPUT | LVTTL | | | | | || LED1_SEG<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED1_SEG<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED1_SEG<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED1_SEG<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED1_SEG<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED1_SEG<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED1_SEG<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED2_SEG<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED2_SEG<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED2_SEG<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED2_SEG<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED2_SEG<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED2_SEG<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED2_SEG<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED3_SEG<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED3_SEG<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED3_SEG<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED3_SEG<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED3_SEG<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED3_SEG<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED3_SEG<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED4_SEG<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED4_SEG<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED4_SEG<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED4_SEG<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED4_SEG<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED4_SEG<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED4_SEG<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED5_SEG<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED5_SEG<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED5_SEG<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED5_SEG<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED5_SEG<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED5_SEG<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED5_SEG<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED6_SEG<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED6_SEG<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED6_SEG<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED6_SEG<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED6_SEG<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED6_SEG<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED6_SEG<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED_gate | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || LED_point<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED_point<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LED_point<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || OVER | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTLATCH | | || RST | IOB | INPUT | LVTTL | | | | | || Switch<0> | IOB | INPUT | LVTTL | | | | | || Switch<1> | IOB | INPUT | LVTTL | | | | | || Switch<2> | IOB | INPUT | LVTTL | | | | | |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details-----------------------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Additional Device Resource Counts----------------------------------------------Number of JTAG Gates for IOBs = 53Number of Equivalent Gates for Design = 1,989Number of RPM Macros = 0Number of Hard Macros = 0PCI IOBs = 0PCI LOGICs = 0CAPTUREs = 0BSCANs = 0STARTUPs = 0DLLs = 0GCLKIOBs = 2GCLKs = 2Block RAMs = 0TBUFs = 0Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 36IOB Latches not driven by LUTs = 1IOB Latches = 1IOB Flip Flops not driven by LUTs = 1IOB Flip Flops = 1Unbonded IOBs = 0Bonded IOBs = 51Shift Registers = 0Static Shift Registers = 0Dynamic Shift Registers = 016x1 ROMs = 016x1 RAMs = 032x1 RAMs = 0Dual Port RAMs = 0MULTANDs = 0MUXF5s + MUXF6s = 134 input LUTs used as Route-Thrus = 464 input LUTs = 173Slice Latches not driven by LUTs = 1Slice Latches = 25Slice Flip Flops not driven by LUTs = 33Slice Flip Flops = 66Slices = 127Number of LUT signals with 4 loads = 10Number of LUT signals with 3 loads = 6Number of LUT signals with 2 loads = 6Number of LUT signals with 1 load = 139NGM Average fanout of LUT = 1.89NGM Maximum fanout of LUT = 26NGM Average fanin for LUT = 3.2254Number of LUT symbols = 173Number of IPAD symbols = 6Number of IBUF symbols = 4⌨️ 快捷键说明
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