control_unite.vhdl

本代码介绍了使用VHDL开发FPGA的一般流程

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Control_Unite is
	PORT(
			Switch			:IN std_logic_vector(0 to 2);	   
			clk1,clk10,clk100	:IN std_logic;
			RST				:IN std_logic;				   
			gate,CLEAR,LOAD   	:OUT std_logic;			    
			LED_point			:OUT std_logic_vector(0 to 2)	   

	);
end Control_Unite;

architecture Behavioral of Control_Unite is
signal clk,S1,S2 				:std_logic:='0';		
begin
	clk<=clk1		when (Switch="011")	Else 
	     clk10 	when (Switch="101")	Else 
		clk100 	when (Switch="110")	Else
		'0';
	process(clk)
		begin
			if rising_edge(clk)		then
				S1<=not S1;
			end if;
			if falling_edge(clk)	then
				S2<=not S2;
			end if;
	end process;		
	LED_point	<="011"		when (Switch="011")	Else 
		       "101"		when (Switch="101")	Else 
			  "110"   	when (Switch="110")	Else
			  "000";	 							--若三个小数点同时亮，表示选择开关出错
	gate<=S1;
	LOAD<='1'		when RST='0'	else
		 (not S1) and S2;		  
	Clear<='0'	when RST='0'	else
		  S1 or S2;
end Behavioral;