freq_counter.npl

来自「本代码介绍了使用VHDL开发FPGA的一般流程」· NPL 代码 · 共 46 行

JDF G
// Created by Project Navigator ver 1.0
PROJECT Freq_counter
DESIGN freq_counter
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s100
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE Top.vhdl
SOURCE bcd2seg_display.vhdl
SOURCE control_unite.vhdl
SOURCE counter.vhdl
SOURCE counter10.vhdl
SOURCE free_change.vhdl
SOURCE gate.vhdl
SOURCE data_lock.vhdl
SOURCE freq_change.vhdl
STIMULUS gate_teat.vhd
STIMULUS freq_change_test.vhd
STIMULUS counter_test.vhd
STIMULUS control_unite_test.vhd
STIMULUS data_lock_test.vhd
STIMULUS counter10_test.vhd
STIMULUS bcd2seg_test.vhd
STIMULUS top_test.vhd
STIMULUS free_change_test.vhd
DEPASSOC top top.ucf
[STATUS-ALL]
top.ncdFile=WARNINGS,1166452836
top.ngcFile=WARNINGS,1166452822
top.ngdFile=WARNINGS,1166452828
[STRATEGY-LIST]
Normal=True