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本代码介绍了使用VHDL开发FPGA的一般流程

    Total                      5.140ns (2.368ns logic, 2.772ns route)
                                       (46.1% logic, 53.9% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'U1_clk36:O'
Delay:               3.385ns (Levels of Logic = 0)
  Source:            U1_S1 (FF)
  Destination:       U1_S1 (FF)
  Source Clock:      U1_clk36:O rising
  Destination Clock: U1_clk36:O rising

  Data Path: U1_S1 to U1_S1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              5   1.085   1.566  U1_S1 (U1_S1)
     FDR:R                     0.734          U1_S1_1
    ----------------------------------------
    Total                      3.385ns (1.819ns logic, 1.566ns route)
                                       (53.7% logic, 46.3% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'U3_U4__n00021:O'
Delay:               6.803ns (Levels of Logic = 5)
  Source:            U3_U5_Q_1 (FF)
  Destination:       U3_U5_Q_3 (FF)
  Source Clock:      U3_U4__n00021:O falling
  Destination Clock: U3_U4__n00021:O falling

  Data Path: U3_U5_Q_1 to U3_U5_Q_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            7   1.085   1.755  U3_U5_Q_1 (U3_U5_Q_1)
     LUT1_L:I0->LO         1   0.549   0.000  U3_U5_Q<1>_rt (U3_U5_Q<1>_rt)
     MUXCY:S->O            1   0.659   0.000  U3_U5_Madd__n0004_inst_cy_1 (U3_U5_Madd__n0004_inst_cy_1)
     MUXCY:CI->O           0   0.042   0.000  U3_U5_Madd__n0004_inst_cy_2 (U3_U5_Madd__n0004_inst_cy_2)
     XORCY:CI->O           1   0.420   1.035  U3_U5_Madd__n0004_inst_sum_3 (U3_U5__n0004<3>)
     LUT2_L:I1->LO         1   0.549   0.000  U3_U5__n0001<3>1 (U3_U5__n0001<3>)
     FDC_1:D                   0.709          U3_U5_Q_3
    ----------------------------------------
    Total                      6.803ns (4.013ns logic, 2.790ns route)
                                       (59.0% logic, 41.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'U3_U3__n00021:O'
Delay:               6.803ns (Levels of Logic = 5)
  Source:            U3_U4_Q_1 (FF)
  Destination:       U3_U4_Q_3 (FF)
  Source Clock:      U3_U3__n00021:O falling
  Destination Clock: U3_U3__n00021:O falling

  Data Path: U3_U4_Q_1 to U3_U4_Q_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            7   1.085   1.755  U3_U4_Q_1 (U3_U4_Q_1)
     LUT1_L:I0->LO         1   0.549   0.000  U3_U4_Q<1>_rt (U3_U4_Q<1>_rt)
     MUXCY:S->O            1   0.659   0.000  U3_U4_Madd__n0004_inst_cy_1 (U3_U4_Madd__n0004_inst_cy_1)
     MUXCY:CI->O           0   0.042   0.000  U3_U4_Madd__n0004_inst_cy_2 (U3_U4_Madd__n0004_inst_cy_2)
     XORCY:CI->O           1   0.420   1.035  U3_U4_Madd__n0004_inst_sum_3 (U3_U4__n0004<3>)
     LUT2_L:I1->LO         1   0.549   0.000  U3_U4__n0001<3>1 (U3_U4__n0001<3>)
     FDC_1:D                   0.709          U3_U4_Q_3
    ----------------------------------------
    Total                      6.803ns (4.013ns logic, 2.790ns route)
                                       (59.0% logic, 41.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'U3_U2__n00021:O'
Delay:               6.803ns (Levels of Logic = 5)
  Source:            U3_U3_Q_1 (FF)
  Destination:       U3_U3_Q_3 (FF)
  Source Clock:      U3_U2__n00021:O falling
  Destination Clock: U3_U2__n00021:O falling

  Data Path: U3_U3_Q_1 to U3_U3_Q_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            7   1.085   1.755  U3_U3_Q_1 (U3_U3_Q_1)
     LUT1_L:I0->LO         1   0.549   0.000  U3_U3_Q<1>_rt (U3_U3_Q<1>_rt)
     MUXCY:S->O            1   0.659   0.000  U3_U3_Madd__n0004_inst_cy_1 (U3_U3_Madd__n0004_inst_cy_1)
     MUXCY:CI->O           0   0.042   0.000  U3_U3_Madd__n0004_inst_cy_2 (U3_U3_Madd__n0004_inst_cy_2)
     XORCY:CI->O           1   0.420   1.035  U3_U3_Madd__n0004_inst_sum_3 (U3_U3__n0004<3>)
     LUT2_L:I1->LO         1   0.549   0.000  U3_U3__n0001<3>1 (U3_U3__n0001<3>)
     FDC_1:D                   0.709          U3_U3_Q_3
    ----------------------------------------
    Total                      6.803ns (4.013ns logic, 2.790ns route)
                                       (59.0% logic, 41.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'U3_U1__n00021:O'
Delay:               6.803ns (Levels of Logic = 5)
  Source:            U3_U2_Q_1 (FF)
  Destination:       U3_U2_Q_3 (FF)
  Source Clock:      U3_U1__n00021:O falling
  Destination Clock: U3_U1__n00021:O falling

  Data Path: U3_U2_Q_1 to U3_U2_Q_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            7   1.085   1.755  U3_U2_Q_1 (U3_U2_Q_1)
     LUT1_L:I0->LO         1   0.549   0.000  U3_U2_Q<1>_rt (U3_U2_Q<1>_rt)
     MUXCY:S->O            1   0.659   0.000  U3_U2_Madd__n0004_inst_cy_1 (U3_U2_Madd__n0004_inst_cy_1)
     MUXCY:CI->O           0   0.042   0.000  U3_U2_Madd__n0004_inst_cy_2 (U3_U2_Madd__n0004_inst_cy_2)
     XORCY:CI->O           1   0.420   1.035  U3_U2_Madd__n0004_inst_sum_3 (U3_U2__n0004<3>)
     LUT2_L:I1->LO         1   0.549   0.000  U3_U2__n0001<3>1 (U3_U2__n0001<3>)
     FDC_1:D                   0.709          U3_U2_Q_3
    ----------------------------------------
    Total                      6.803ns (4.013ns logic, 2.790ns route)
                                       (59.0% logic, 41.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'U3_U0__n00021:O'
Delay:               6.803ns (Levels of Logic = 5)
  Source:            U3_U1_Q_1 (FF)
  Destination:       U3_U1_Q_3 (FF)
  Source Clock:      U3_U0__n00021:O falling
  Destination Clock: U3_U0__n00021:O falling

  Data Path: U3_U1_Q_1 to U3_U1_Q_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            7   1.085   1.755  U3_U1_Q_1 (U3_U1_Q_1)
     LUT1_L:I0->LO         1   0.549   0.000  U3_U1_Q<1>_rt (U3_U1_Q<1>_rt)
     MUXCY:S->O            1   0.659   0.000  U3_U1_Madd__n0004_inst_cy_1 (U3_U1_Madd__n0004_inst_cy_1)
     MUXCY:CI->O           0   0.042   0.000  U3_U1_Madd__n0004_inst_cy_2 (U3_U1_Madd__n0004_inst_cy_2)
     XORCY:CI->O           1   0.420   1.035  U3_U1_Madd__n0004_inst_sum_3 (U3_U1__n0004<3>)
     LUT2_L:I1->LO         1   0.549   0.000  U3_U1__n0001<3>1 (U3_U1__n0001<3>)
     FDC_1:D                   0.709          U3_U1_Q_3
    ----------------------------------------
    Total                      6.803ns (4.013ns logic, 2.790ns route)
                                       (59.0% logic, 41.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'U2_CP1:O'
Delay:               6.803ns (Levels of Logic = 5)
  Source:            U3_U0_Q_1 (FF)
  Destination:       U3_U0_Q_3 (FF)
  Source Clock:      U2_CP1:O falling
  Destination Clock: U2_CP1:O falling

  Data Path: U3_U0_Q_1 to U3_U0_Q_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            7   1.085   1.755  U3_U0_Q_1 (U3_U0_Q_1)
     LUT1_L:I0->LO         1   0.549   0.000  U3_U0_Q<1>_rt (U3_U0_Q<1>_rt)
     MUXCY:S->O            1   0.659   0.000  U3_U0_Madd__n0004_inst_cy_1 (U3_U0_Madd__n0004_inst_cy_1)
     MUXCY:CI->O           0   0.042   0.000  U3_U0_Madd__n0004_inst_cy_2 (U3_U0_Madd__n0004_inst_cy_2)
     XORCY:CI->O           1   0.420   1.035  U3_U0_Madd__n0004_inst_sum_3 (U3_U0__n0004<3>)
     LUT2_L:I1->LO         1   0.549   0.000  U3_U0__n0001<3>1 (U3_U0__n0001<3>)
     FDC_1:D                   0.709          U3_U0_Q_3
    ----------------------------------------
    Total                      6.803ns (4.013ns logic, 2.790ns route)
                                       (59.0% logic, 41.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'U1_clk36:O'
Offset:              6.788ns (Levels of Logic = 1)
  Source:            U1_S1_1 (FF)
  Destination:       LED_gate (PAD)
  Source Clock:      U1_clk36:O rising

  Data Path: U1_S1_1 to LED_gate
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   1.085   1.035  U1_S1_1 (U1_S1_1)
     OBUF:I->O                 4.668          LED_gate_OBUF (LED_gate)
    ----------------------------------------
    Total                      6.788ns (5.753ns logic, 1.035ns route)
                                       (84.8% logic, 15.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'U1_LOAD1:O'
Offset:              25.841ns (Levels of Logic = 12)
  Source:            U4_BCD_2_0 (LATCH)
  Destination:       LED3_SEG<6> (PAD)
  Source Clock:      U1_LOAD1:O falling

  Data Path: U4_BCD_2_0 to LED3_SEG<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               2   1.194   1.206  U4_BCD_2_0 (U4_BCD_2_0)
     LUT4:I2->O            1   0.549   1.035  U5_hide35 (CHOICE198)
     LUT4:I3->O            1   0.549   1.035  U5_hide48 (CHOICE200)
     LUT4:I3->O            1   0.549   1.035  U5_hide105_SW0 (N8019)
     LUT4:I2->O            1   0.549   1.035  U5_hide105 (CHOICE208)
     LUT4:I3->O            1   0.549   1.035  U5_hide182_SW0 (N8023)
     LUT4:I2->O            1   0.549   1.035  U5_hide182 (CHOICE216)
     LUT3:I2->O            1   0.549   1.035  U5_hide219 (CHOICE219)
     LUT4:I3->O            1   0.549   1.035  U5_hide302_SW0 (N8015)
     LUT4:I3->O            7   0.549   1.755  U5_hide302 (CHOICE232)
     LUT4:I0->O            6   0.549   1.665  U5_SEG<1> (U5_SEG<1>)
     LUT4:I3->O            1   0.549   1.035  U5_SEG_6<1>1 (LED6_SEG_1_OBUF)
     OBUF:I->O                 4.668          LED6_SEG_1_OBUF (LED6_SEG<1>)
    ----------------------------------------
    Total                     25.841ns (11.900ns logic, 13.941ns route)
                                       (46.1% logic, 53.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'U0_U0_clk_out:Q'
Offset:              29.072ns (Levels of Logic = 12)
  Source:            U5_S_0_1 (FF)
  Destination:       LED3_SEG<6> (PAD)
  Source Clock:      U0_U0_clk_out:Q rising

  Data Path: U5_S_0_1 to LED3_SEG<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             57   1.085   4.545  U5_S_0_1 (U5_S_0_1)
     LUT4:I1->O            1   0.549   1.035  U5_hide35 (CHOICE198)
     LUT4:I3->O            1   0.549   1.035  U5_hide48 (CHOICE200)
     LUT4:I3->O            1   0.549   1.035  U5_hide105_SW0 (N8019)
     LUT4:I2->O            1   0.549   1.035  U5_hide105 (CHOICE208)
     LUT4:I3->O            1   0.549   1.035  U5_hide182_SW0 (N8023)
     LUT4:I2->O            1   0.549   1.035  U5_hide182 (CHOICE216)
     LUT3:I2->O            1   0.549   1.035  U5_hide219 (CHOICE219)
     LUT4:I3->O            1   0.549   1.035  U5_hide302_SW0 (N8015)
     LUT4:I3->O            7   0.549   1.755  U5_hide302 (CHOICE232)
     LUT4:I0->O            6   0.549   1.665  U5_SEG<1> (U5_SEG<1>)
     LUT4:I3->O            1   0.549   1.035  U5_SEG_6<1>1 (LED6_SEG_1_OBUF)
     OBUF:I->O                 4.668          LED6_SEG_1_OBUF (LED6_SEG<1>)
    ----------------------------------------
    Total                     29.072ns (11.792ns logic, 17.280ns route)
                                       (40.6% logic, 59.4% route)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               8.594ns (Levels of Logic = 3)
  Source:            Switch<2> (PAD)
  Destination:       LED_point<0> (PAD)

  Data Path: Switch<2> to LED_point<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             5   0.776   1.566  Switch_2_IBUF (Switch_2_IBUF)
     LUT3:I1->O            1   0.549   1.035  U1_LED_point<1>1 (LED_point_1_OBUF)
     OBUF:I->O                 4.668          LED_point_1_OBUF (LED_point<1>)
    ----------------------------------------
    Total                      8.594ns (5.993ns logic, 2.601ns route)
                                       (69.7% logic, 30.3% route)

=========================================================================
CPU : 4.97 / 5.98 s | Elapsed : 5.00 / 6.00 s
 
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Total memory usage is 61992 kilobytes