top.syr

本代码介绍了使用VHDL开发FPGA的一般流程

=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 6
 16x4-bit ROM                      : 6
# Adders/Subtractors               : 6
 4-bit adder                       : 6
# Counters                         : 6
 3-bit up counter                  : 1
 12-bit up counter                 : 1
 4-bit up counter                  : 4
# Registers                        : 14
 1-bit register                    : 8
 4-bit register                    : 6
# Latches                          : 7
 1-bit latch                       : 1
 4-bit latch                       : 6
# Comparators                      : 12
 4-bit comparator less             : 5
 12-bit comparator less            : 1
 5-bit comparator less             : 6
# Multiplexers                     : 1
 4-bit 8-to-1 multiplexer          : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <top> ...

Optimizing unit <Control_Unite> ...

Optimizing unit <counter10> ...

Optimizing unit <BCD2SEG_Display> ...
Loading device for application Xst from file 'v100.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 12.
FlipFlop U5_S_0 has been replicated 1 time(s)
FlipFlop U5_S_1 has been replicated 1 time(s)
FlipFlop U5_S_2 has been replicated 1 time(s)
FlipFlop U1_S1 has been replicated 1 time(s) to handle iob=true attribute.
Latch U4_OVER has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : top.ngr
Top Level Output File Name         : top
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 53

Macro Statistics :
# Registers                        : 14
#      1-bit register              : 7
#      3-bit register              : 7
# Multiplexers                     : 1
#      4-bit 8-to-1 multiplexer    : 1
# Comparators                      : 6
#      12-bit comparator less      : 1
#      4-bit comparator less       : 5

Cell Usage :
# BELS                             : 309
#      GND                         : 1
#      LUT1                        : 30
#      LUT1_L                      : 24
#      LUT2                        : 15
#      LUT2_D                      : 1
#      LUT2_L                      : 18
#      LUT3                        : 32
#      LUT3_D                      : 1
#      LUT4                        : 89
#      LUT4_D                      : 6
#      MUXCY                       : 41
#      MUXF5                       : 5
#      MUXF6                       : 4
#      VCC                         : 1
#      XORCY                       : 41
# FlipFlops/Latches                : 93
#      FDC_1                       : 24
#      FDP_1                       : 1
#      FDR                         : 36
#      FDR_1                       : 1
#      FDS                         : 5
#      LD                          : 26
# Clock Buffers                    : 2
#      BUFGP                       : 2
# IO Buffers                       : 51
#      IBUF                        : 4
#      OBUF                        : 47
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100pq208-6 

 Number of Slices:                     136  out of   1200    11%  
 Number of Slice Flip Flops:            93  out of   2400     3%  
 Number of 4 input LUTs:               216  out of   2400     9%  
 Number of bonded IOBs:                 51  out of    144    35%  
 Number of GCLKs:                        2  out of      4    50%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
LOAD(U1_LOAD1:O)                   | NONE(*)(U4_BCD_2_2)    | 26    |
U3_carry(U3_U5__n00021:O)          | NONE(*)(U3_OVER)       | 1     |
U0_shift_change2_clk_out:Q         | NONE                   | 5     |
U0_shift_change1_clk_out:Q         | NONE                   | 5     |
CLK_Basic                          | BUFGP                  | 13    |
U0_U0_clk_out:Q                    | NONE                   | 11    |
U0_shift_change0_clk_out:Q         | NONE                   | 5     |
U1_clk(U1_clk36:O)                 | NONE(*)(U1_S2)         | 3     |
U3_S5(U3_U4__n00021:O)             | NONE(*)(U3_U5_Q_2)     | 4     |
U3_S4(U3_U3__n00021:O)             | NONE(*)(U3_U4_Q_2)     | 4     |
U3_S3(U3_U2__n00021:O)             | NONE(*)(U3_U3_Q_3)     | 4     |
U3_S2(U3_U1__n00021:O)             | NONE(*)(U3_U2_Q_1)     | 4     |
U3_S1(U3_U0__n00021:O)             | NONE(*)(U3_U1_Q_3)     | 4     |
CP(U2_CP1:O)                       | NONE(*)(U3_U0_Q_1)     | 4     |
-----------------------------------+------------------------+-------+
(*) These 9 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 6.803ns (Maximum Frequency: 146.994MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 29.072ns
   Maximum combinational path delay: 8.594ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'U0_shift_change2_clk_out:Q'
Delay:               5.140ns (Levels of Logic = 1)
  Source:            U0_shift_change3_count_3 (FF)
  Destination:       U0_shift_change3_count_3 (FF)
  Source Clock:      U0_shift_change2_clk_out:Q rising
  Destination Clock: U0_shift_change2_clk_out:Q rising

  Data Path: U0_shift_change3_count_3 to U0_shift_change3_count_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              3   1.085   1.332  U0_shift_change3_count_3 (U0_shift_change3_count_3)
     LUT3:I0->O            4   0.549   1.440  U0_shift_change3__n00051 (U0_shift_change3__n0005)
     FDR:R                     0.734          U0_shift_change3_count_2
    ----------------------------------------
    Total                      5.140ns (2.368ns logic, 2.772ns route)
                                       (46.1% logic, 53.9% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'U0_shift_change1_clk_out:Q'
Delay:               5.140ns (Levels of Logic = 1)
  Source:            U0_shift_change2_count_3 (FF)
  Destination:       U0_shift_change2_count_3 (FF)
  Source Clock:      U0_shift_change1_clk_out:Q rising
  Destination Clock: U0_shift_change1_clk_out:Q rising

  Data Path: U0_shift_change2_count_3 to U0_shift_change2_count_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              3   1.085   1.332  U0_shift_change2_count_3 (U0_shift_change2_count_3)
     LUT3:I0->O            4   0.549   1.440  U0_shift_change2__n00051 (U0_shift_change2__n0005)
     FDR:R                     0.734          U0_shift_change2_count_2
    ----------------------------------------
    Total                      5.140ns (2.368ns logic, 2.772ns route)
                                       (46.1% logic, 53.9% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'CLK_Basic'
Delay:               6.383ns (Levels of Logic = 2)
  Source:            U0_U0_count_10 (FF)
  Destination:       U0_U0_count_7 (FF)
  Source Clock:      CLK_Basic rising
  Destination Clock: CLK_Basic rising

  Data Path: U0_U0_count_10 to U0_U0_count_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   1.085   1.206  U0_U0_count_10 (U0_U0_count_10)
     LUT2_D:I0->LO         1   0.549   0.100  U0_U0_Mcompar__n0002_ALB_SW0 (N8124)
     LUT4:I0->O           12   0.549   2.160  U0_U0__n00051 (U0_U0__n0005)
     FDR:R                     0.734          U0_U0_count_10
    ----------------------------------------
    Total                      6.383ns (2.917ns logic, 3.466ns route)
                                       (45.7% logic, 54.3% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'U0_U0_clk_out:Q'
Delay:               5.563ns (Levels of Logic = 1)
  Source:            U5_S_0 (FF)
  Destination:       U5_S_1 (FF)
  Source Clock:      U0_U0_clk_out:Q rising
  Destination Clock: U0_U0_clk_out:Q rising

  Data Path: U5_S_0 to U5_S_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              7   1.085   1.755  U5_S_0 (U5_S_0)
     LUT3_D:I2->O          4   0.549   1.440  U5__n00511 (U5__n0051)
     FDR:R                     0.734          U5_S_2_1
    ----------------------------------------
    Total                      5.563ns (2.368ns logic, 3.195ns route)
                                       (42.6% logic, 57.4% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'U0_shift_change0_clk_out:Q'
Delay:               5.140ns (Levels of Logic = 1)
  Source:            U0_shift_change1_count_3 (FF)
  Destination:       U0_shift_change1_count_3 (FF)
  Source Clock:      U0_shift_change0_clk_out:Q rising
  Destination Clock: U0_shift_change0_clk_out:Q rising

  Data Path: U0_shift_change1_count_3 to U0_shift_change1_count_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              3   1.085   1.332  U0_shift_change1_count_3 (U0_shift_change1_count_3)
     LUT3:I0->O            4   0.549   1.440  U0_shift_change1__n00051 (U0_shift_change1__n0005)
     FDR:R                     0.734          U0_shift_change1_count_2
    ----------------------------------------