top.syr

本代码介绍了使用VHDL开发FPGA的一般流程

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : top.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : top
Output Format                      : NGC
Target Device                      : xc2s100-6-pq208

---- Source Options
Top Module Name                    : top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : top.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file E:/lvbin/Freq_counter/counter10.vhdl in Library work.
Entity <counter10> (Architecture <Behavioral>) compiled.
Compiling vhdl file E:/lvbin/Freq_counter/free_change.vhdl in Library work.
Entity <Free_Change> (Architecture <Behavioral>) compiled.
Compiling vhdl file E:/lvbin/Freq_counter/freq_change.vhdl in Library work.
Entity <Freq_Change> (Architecture <Behavioral>) compiled.
Compiling vhdl file E:/lvbin/Freq_counter/control_unite.vhdl in Library work.
Entity <Control_Unite> (Architecture <Behavioral>) compiled.
Compiling vhdl file E:/lvbin/Freq_counter/gate.vhdl in Library work.
Entity <GATE> (Architecture <Behavioral>) compiled.
Compiling vhdl file E:/lvbin/Freq_counter/counter.vhdl in Library work.
Entity <Counter> (Architecture <Behavioral>) compiled.
Compiling vhdl file E:/lvbin/Freq_counter/data_lock.vhdl in Library work.
Entity <Data_Lock> (Architecture <Behavioral>) compiled.
Compiling vhdl file E:/lvbin/Freq_counter/bcd2seg_display.vhdl in Library work.
Entity <BCD2SEG_Display> (Architecture <Behavioral>) compiled.
Compiling vhdl file E:/lvbin/Freq_counter/Top.vhdl in Library work.
Entity <Top> (Architecture <behavior>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top> (Architecture <behavior>).
    Set property "buffer_type = bufGP" for signal <CLK> in unit <top>.
Entity <top> analyzed. Unit <top> generated.

Analyzing Entity <Freq_Change> (Architecture <behavioral>).
    Set property "buffer_type = ibuf" for signal <clk_in> in unit <Free_Change>.
    Set property "buffer_type = ibuf" for signal <clk_in> in unit <Free_Change0_>.
    Set property "buffer_type = ibuf" for signal <clk_in> in unit <Free_Change0_> (previous value was "ibuf").
    Set property "buffer_type = ibuf" for signal <clk_in> in unit <Free_Change0_> (previous value was "ibuf").
    Set property "buffer_type = ibuf" for signal <clk_in> in unit <Free_Change0_> (previous value was "ibuf").
Entity <Freq_Change> analyzed. Unit <Freq_Change> generated.

Analyzing generic Entity <Free_Change> (Architecture <behavioral>).
	rate = 3200
    Set property "buffer_type = ibuf" for signal <clk_in> in unit <Free_Change> (previous value was "ibuf").
Entity <Free_Change> analyzed. Unit <Free_Change> generated.

Analyzing generic Entity <Free_Change> (Architecture <behavioral>).
	rate = 10
    Set property "buffer_type = ibuf" for signal <clk_in> in unit <Free_Change0_> (previous value was "ibuf").
Entity <Free_Change> analyzed. Unit <Free_Change0> generated.

Analyzing Entity <Control_Unite> (Architecture <behavioral>).
Entity <Control_Unite> analyzed. Unit <Control_Unite> generated.

Analyzing Entity <GATE> (Architecture <behavioral>).
Entity <GATE> analyzed. Unit <GATE> generated.

Analyzing Entity <Counter> (Architecture <behavioral>).
Entity <Counter> analyzed. Unit <Counter> generated.

Analyzing Entity <counter10> (Architecture <behavioral>).
Entity <counter10> analyzed. Unit <counter10> generated.

Analyzing Entity <Data_Lock> (Architecture <behavioral>).
WARNING:Xst:819 - E:/lvbin/Freq_counter/data_lock.vhdl line 23: The following signals are missing in the process sensitivity list:
   F, E, D, C, B, A, OVER_in.
Entity <Data_Lock> analyzed. Unit <Data_Lock> generated.

Analyzing Entity <BCD2SEG_Display> (Architecture <behavioral>).
Entity <BCD2SEG_Display> analyzed. Unit <BCD2SEG_Display> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <counter10>.
    Related source file is E:/lvbin/Freq_counter/counter10.vhdl.
    Found 16x4-bit ROM for signal <count_BCD_out>.
    Found 5-bit comparator less for signal <$n0003> created at line 28.
    Found 4-bit adder for signal <$n0004> created at line 29.
    Found 4-bit register for signal <Q>.
    Summary:
	inferred   1 ROM(s).
	inferred   4 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <counter10> synthesized.


Synthesizing Unit <Free_Change0>.
    Related source file is E:/lvbin/Freq_counter/free_change.vhdl.
    Found 1-bit register for signal <clk_out>.
    Found 4-bit comparator less for signal <$n0002> created at line 27.
    Found 4-bit up counter for signal <count>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <Free_Change0> synthesized.


Synthesizing Unit <Free_Change>.
    Related source file is E:/lvbin/Freq_counter/free_change.vhdl.
    Found 1-bit register for signal <clk_out>.
    Found 12-bit comparator less for signal <$n0002> created at line 27.
    Found 12-bit up counter for signal <count>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <Free_Change> synthesized.


Synthesizing Unit <BCD2SEG_Display>.
    Related source file is E:/lvbin/Freq_counter/bcd2seg_display.vhdl.
    Found 4-bit comparator less for signal <$n0029> created at line 28.
    Found 4-bit 8-to-1 multiplexer for signal <DB>.
    Found 3-bit up counter for signal <S>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 Comparator(s).
	inferred   4 Multiplexer(s).
Unit <BCD2SEG_Display> synthesized.


Synthesizing Unit <Data_Lock>.
    Related source file is E:/lvbin/Freq_counter/data_lock.vhdl.
WARNING:Xst:737 - Found 4-bit latch for signal <BCD_6>.
WARNING:Xst:737 - Found 4-bit latch for signal <BCD_5>.
WARNING:Xst:737 - Found 4-bit latch for signal <BCD_4>.
WARNING:Xst:737 - Found 4-bit latch for signal <BCD_3>.
WARNING:Xst:737 - Found 4-bit latch for signal <BCD_2>.
WARNING:Xst:737 - Found 4-bit latch for signal <BCD_1>.
WARNING:Xst:737 - Found 1-bit latch for signal <OVER>.
Unit <Data_Lock> synthesized.


Synthesizing Unit <Counter>.
    Related source file is E:/lvbin/Freq_counter/counter.vhdl.
    Found 1-bit register for signal <OVER>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <Counter> synthesized.


Synthesizing Unit <GATE>.
    Related source file is E:/lvbin/Freq_counter/gate.vhdl.
Unit <GATE> synthesized.


Synthesizing Unit <Control_Unite>.
    Related source file is E:/lvbin/Freq_counter/control_unite.vhdl.
    Found 1-bit register for signal <S1>.
    Found 1-bit register for signal <S2>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <Control_Unite> synthesized.


Synthesizing Unit <Freq_Change>.
    Related source file is E:/lvbin/Freq_counter/freq_change.vhdl.
Unit <Freq_Change> synthesized.


Synthesizing Unit <top>.
    Related source file is E:/lvbin/Freq_counter/Top.vhdl.
Unit <top> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *