📄 command.v
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/******************************************************************************
*
* LOGIC CORE: Command module
* MODULE NAME: command()
* COMPANY: Northwest Logic Design, Inc.
* www.nwlogic.com
*
* REVISION HISTORY:
*
* Revision 1.0 05/11/2000 Description: Initial Release.
* 1.1 07/10/2000 Description: change precharge to terminate
* for full page accesses.
*
* FUNCTIONAL DESCRIPTION:
*
* This module is the command processor module for the SDR SDRAM controller.
*
* Copyright Northwest Logic, Inc., 2000. All rights reserved.
******************************************************************************/
/*The command module accepts decoded commands from the control interface module, refresh requests from the
refresh control logic, and generates the appropriate commands to the SDRAM. The module contains a simple arbiter
that arbitrates between the commands from the host interface and the refresh requests from the refresh control logic.
The refresh requests from the refresh control logic have priority over the commands from the host interface. If a com-
mand from the host arrives at the same time or during a hidden refresh operation, the arbiter holds off the host by not
asserting CMDACK until the hidden refresh operation is complete. If a hidden refresh command is received while a
host operation is in progress, the hidden refresh is held off until the host operation is complete.
*/
module command(
CLK,
RESET_N,
SADDR,
NOP,
READA,
WRITEA,
REFRESH,
PRECHARGE,
LOAD_MODE,
SC_CL,
SC_RC,
SC_RRD,
SC_PM,
SC_BL,
REF_REQ,
REF_ACK,
CM_ACK,
OE,
SA,
BA,
CS_N,
CKE,
RAS_N,
CAS_N,
WE_N
);
`include "params.v"
input CLK; // System Clock 模块的系统时钟
input RESET_N; // System Reset 模块复位信号
input [`ASIZE-1:0] SADDR; // Address 地址输入（从control_interface模块输入）
input NOP; // Decoded NOP command 解码后的NOP命令（从control_interface模块输入）
input READA; // Decoded READA command 解码后的READA命令（从control_interface模块输入）
input WRITEA; // Decoded WRITEA command 解码后的WRITEA命令（从control_interface模块输入）
input REFRESH; // Decoded REFRESH command 解码后的REFRESH命令（从control_interface模块输入）
input PRECHARGE; // Decoded PRECHARGE command 解码后的PRECHARGE命令（从control_interface模块输入）
input LOAD_MODE; // Decoded LOAD_MODE command 解码后的LOAD_MODE命令（从control_interface模块输入）
input [1:0] SC_CL; // Programmed CAS latency 编程的CAS传输延迟（从control_interface模块输入）
input [1:0] SC_RC; // Programmed RC delay 编程的RAS to CAS Delay（从control_interface模块输入）
input [3:0] SC_RRD; // Programmed RRD delay 编程的RRD延迟（从control_interface模块输入）
input SC_PM; // programmed Page Mode 编程的Page Mode（从control_interface模块输入）
input [3:0] SC_BL; // Programmed burst length 编程的burst length（从control_interface模块输入）
input REF_REQ; // Hidden refresh request 隐藏的刷新请求信号（从control_interface模块输入）
output REF_ACK; // Refresh request acknowledge 刷新请求确认信号（输出给control_interface模块）
output CM_ACK; // Command acknowledge 命令确认信号（输出给control_interface模块）
output OE; // OE signal for data path module 输出使能信号（输出给data path module）
output [11:0] SA; // SDRAM address SDRAM地址输出，输出给顶层模块sdr_sdram
output [1:0] BA; // SDRAM bank address SDRAM bank选择输出，输出给顶层模块sdr_sdram
output [1:0] CS_N; // SDRAM chip selects SDRAM 片选信号输出，输出给顶层模块sdr_sdram
output CKE; // SDRAM clock enable SDRAM 时钟使能输出，输出给顶层模块sdr_sdram
output RAS_N; // SDRAM RAS SDRAM 行地址选通输出，输出给顶层模块sdr_sdram
output CAS_N; // SDRAM CAS SDRAM 列地址选通输出，输出给顶层模块sdr_sdram
output WE_N; // SDRAM WE_N SDRAM 写操作使能输出，输出给顶层模块sdr_sdram
reg CM_ACK;
reg REF_ACK;
reg OE;
reg [11:0] SA;
reg [1:0] BA;
reg [1:0] CS_N;
reg CKE;
reg RAS_N;
reg CAS_N;
reg WE_N;
// Internal signals
reg do_nop;
reg do_reada;
reg do_writea;
reg do_writea1;
reg do_refresh;
reg do_precharge;
reg do_load_mode; //内部命令信号，在接收到control_interface模块输入的命令之后，如果SDRAM空闲，则这些内部命令信号有效
reg command_done; //标志SDRAM正在运行命令的信号，1表示命令正在运行，0表示空闲
reg [7:0] command_delay; //命令延迟移位寄存器，确保SDRAM有足够时间完成上一个命令操作
reg [3:0] rw_shift; //读写移位寄存器，用于跟踪ACTIVATE命令和接下来的WRITEA or READA命令之间的间隔时间
reg do_act; //？？
reg rw_flag; //读写标志，用于得到写使能信号WE_N（仅用于读写命令中获得WE_N，其他命令中的WE_N不用该标志信号得出）
reg do_rw; //内部读写触发信号，1表示可触发一次读写操作，0表示尚不能触发读写操作
reg [7:0] oe_shift; //输出使能信号移位寄存器
reg oe1;
reg oe2;
reg oe3;
reg oe4; //这4个信号用于逐级缓存ACTIVATE命令执行时产生的输出使能信号oe1，根据RAS to CAS Delay对其进行延迟，使得WRITE命令有效时，OE有效，从而要写入SDRAM中的数据能同时出现在数据总线上。当进行写命令时，首先执行ACTIVATE命令，行地址有效，激活相应的行；然后经过RAS to CAS Delay（从行地址有效到列地址有效的延迟时间）个时钟周期，执行写命令，列地址有效。由于所写的数据与写命令要同时出现，即在列地址有效时数据必须出现在数据总线上，因此必须将输出使能信号与写命令对齐，即当ACTIVATE命令执行后，延迟RAS to CAS Delay个时钟周期，给出输出使能信号oe，保证数据能及时出现在数据总线上。
reg [3:0] rp_shift; //附加的移位寄存器，用于读、写、刷新命令，使SDRAM有足够时间完成上一个读、写、刷新命令操作
reg rp_done; //标志SDRAM正在继续运行读、写、刷新命令的信号，1表示命令正在继续运行，0表示空闲
wire [`ROWSIZE - 1:0] rowaddr; //内部wire型变量，用于接收从control_interface模块输入的行地址信号
wire [`COLSIZE - 1:0] coladdr; //内部wire型变量，用于接收从control_interface模块输入的列地址信号
wire [`BANKSIZE - 1:0] bankaddr; //内部wire型变量，用于接收从control_interface模块输入的bank选择地址信号
assign rowaddr = SADDR[`ROWSTART + `ROWSIZE - 1: `ROWSTART]; // assignment of the row address bits from SADDR获得行地址
assign coladdr = SADDR[`COLSTART + `COLSIZE - 1:`COLSTART]; // assignment of the column address bits from SADDR获得列地址
assign bankaddr = SADDR[`BANKSTART + `BANKSIZE - 1:`BANKSTART]; // assignment of the bank address bits from SADDR获得bank选择地址
// This always block monitors the individual command lines and issues a command
// to the next stage if there currently another command already running.
//这个always块监测独立的命令线，如果已有命令在运行，则将新的命令推后执行（时钟信号CLK上升沿)
always @(posedge CLK or negedge RESET_N)
begin
if (RESET_N == 0) //复位将命令信号和命令延迟移位寄存器、附加寄存器、SDRAM忙标志等都清0
begin
do_nop <= 0;
do_reada <= 0;
do_writea <= 0;
do_refresh <= 0;
do_precharge <= 0;
do_load_mode <= 0;
command_done <= 0;
command_delay <= 0;
rw_flag <= 0;
rp_shift <= 0;
rp_done <= 0;
end
else
begin
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