system1.hier_info

用VHDL语言实现的控制DS18B20构成测温仪表的程序

|system1
dq[0] <= lpm_bustri:lpm_bustri_component.tridata[0]
clock => \subclk_1us:temp[2].CLK
clock => \subclk_1us:temp[1].CLK
clock => \subclk_1us:temp[0].CLK
clock => clk_1u.CLK
clock => \subclk_1us:temp[3].CLK
closedots[0] <= <VCC>
closedots[1] <= <VCC>
closedots[2] <= <VCC>
closedots[3] <= <VCC>
closedots[4] <= <VCC>
closedots[5] <= <VCC>
closedots[6] <= <VCC>
closedots[7] <= <VCC>
bitvector[0] <= led_convertor:display_component.bitvector[0]
bitvector[1] <= led_convertor:display_component.bitvector[1]
bitvector[2] <= led_convertor:display_component.bitvector[2]
bitvector[3] <= led_convertor:display_component.bitvector[3]
bitvector[4] <= led_convertor:display_component.bitvector[4]
bitvector[5] <= led_convertor:display_component.bitvector[5]
bitvector[6] <= led_convertor:display_component.bitvector[6]
bitvector[7] <= led_convertor:display_component.bitvector[7]
wordselect[0] <= led_convertor:display_component.wordselect[0]
wordselect[1] <= led_convertor:display_component.wordselect[1]
wordselect[2] <= led_convertor:display_component.wordselect[2]
wordselect[3] <= led_convertor:display_component.wordselect[3]
wordselect[4] <= led_convertor:display_component.wordselect[4]
wordselect[5] <= led_convertor:display_component.wordselect[5]


|system1|lpm_bustri:lpm_bustri_component
tridata[0] <= dout[0]
data[0] => dout[0].DATAIN
enabletr => din[0].OE
enabledt => dout[0].OE
result[0] <= din[0].DB_MAX_OUTPUT_PORT_TYPE


|system1|led_convertor:display_component
clock => \mydivider:temp0[6].CLK
clock => \mydivider:temp0[5].CLK
clock => \mydivider:temp0[4].CLK
clock => \mydivider:temp0[3].CLK
clock => \mydivider:temp0[2].CLK
clock => \mydivider:temp0[1].CLK
clock => \mydivider:temp0[0].CLK
clock => clk_1k.CLK
clock => \mydivider:temp0[7].CLK
gate => fsm3~0.IN1
temperaturein[0] => convertor:my_convert.indata[0]
temperaturein[1] => convertor:my_convert.indata[1]
temperaturein[2] => convertor:my_convert.indata[2]
temperaturein[3] => convertor:my_convert.indata[3]
temperaturein[4] => convertor:my_convert.indata[4]
temperaturein[5] => convertor:my_convert.indata[5]
temperaturein[6] => convertor:my_convert.indata[6]
temperaturein[7] => convertor:my_convert.indata[7]
temperaturein[8] => convertor:my_convert.indata[8]
temperaturein[9] => convertor:my_convert.indata[9]
temperaturein[10] => convertor:my_convert.indata[10]
bitvector[0] <= bitvector[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bitvector[1] <= bitvector[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bitvector[2] <= bitvector[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bitvector[3] <= bitvector[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bitvector[4] <= bitvector[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bitvector[5] <= bitvector[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bitvector[6] <= bitvector[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bitvector[7] <= bitvector[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wordselect[0] <= wordselect[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wordselect[1] <= wordselect[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wordselect[2] <= wordselect[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wordselect[3] <= wordselect[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wordselect[4] <= wordselect[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wordselect[5] <= wordselect[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|system1|led_convertor:display_component|convertor:my_convert
indata[0] => temp1~0.OUTPUTSELECT
indata[0] => temp1~1.OUTPUTSELECT
indata[0] => temp1~2.OUTPUTSELECT
indata[0] => temp1~3.OUTPUTSELECT
indata[0] => temp2~0.OUTPUTSELECT
indata[0] => temp2~1.OUTPUTSELECT
indata[0] => temp2~2.OUTPUTSELECT
indata[0] => temp2~3.OUTPUTSELECT
indata[0] => temp3~0.OUTPUTSELECT
indata[0] => temp3~1.OUTPUTSELECT
indata[0] => temp3~2.OUTPUTSELECT
indata[0] => temp3~3.OUTPUTSELECT
indata[0] => temp1[4].ENA
indata[1] => temp2~4.OUTPUTSELECT
indata[1] => temp2~5.OUTPUTSELECT
indata[1] => temp2~6.OUTPUTSELECT
indata[1] => temp2~7.OUTPUTSELECT
indata[1] => temp2~8.OUTPUTSELECT
indata[1] => temp3~4.OUTPUTSELECT
indata[1] => temp3~5.OUTPUTSELECT
indata[1] => temp3~6.OUTPUTSELECT
indata[1] => temp3~7.OUTPUTSELECT
indata[1] => temp4~0.OUTPUTSELECT
indata[1] => temp4~1.OUTPUTSELECT
indata[1] => temp4~2.OUTPUTSELECT
indata[1] => temp4~3.OUTPUTSELECT
indata[1] => temp4~4.OUTPUTSELECT
indata[2] => temp3~12.OUTPUTSELECT
indata[2] => temp3~13.OUTPUTSELECT
indata[2] => temp3~14.OUTPUTSELECT
indata[2] => temp3~15.OUTPUTSELECT
indata[2] => temp3~16.OUTPUTSELECT
indata[2] => temp4~10.OUTPUTSELECT
indata[2] => temp4~11.OUTPUTSELECT
indata[2] => temp4~12.OUTPUTSELECT
indata[2] => temp4~13.OUTPUTSELECT
indata[2] => temp4~14.OUTPUTSELECT
indata[3] => temp4~15.OUTPUTSELECT
indata[3] => temp4~16.OUTPUTSELECT
indata[3] => temp4~17.OUTPUTSELECT
indata[3] => temp4~18.OUTPUTSELECT
indata[3] => temp4~19.OUTPUTSELECT
indata[4] => temp5~0.OUTPUTSELECT
indata[4] => temp5~1.OUTPUTSELECT
indata[4] => temp5~2.OUTPUTSELECT
indata[4] => temp5~3.OUTPUTSELECT
indata[4] => temp5~4.OUTPUTSELECT
indata[5] => temp5~5.OUTPUTSELECT
indata[5] => temp5~6.OUTPUTSELECT
indata[5] => temp5~7.OUTPUTSELECT
indata[5] => temp5~8.OUTPUTSELECT
indata[6] => temp5~9.OUTPUTSELECT
indata[6] => temp5~10.OUTPUTSELECT
indata[6] => temp5~11.OUTPUTSELECT
indata[7] => temp5~16.OUTPUTSELECT
indata[7] => temp5~17.OUTPUTSELECT
indata[7] => temp5~18.OUTPUTSELECT
indata[7] => temp5~19.OUTPUTSELECT
indata[7] => temp6~5.OUTPUTSELECT
indata[7] => temp6~6.OUTPUTSELECT
indata[7] => temp6~7.OUTPUTSELECT
indata[7] => temp6~8.OUTPUTSELECT
indata[7] => temp6~9.OUTPUTSELECT
indata[8] => temp5~24.OUTPUTSELECT
indata[8] => temp5~25.OUTPUTSELECT
indata[8] => temp5~26.OUTPUTSELECT
indata[8] => temp5~27.OUTPUTSELECT
indata[8] => temp6~15.OUTPUTSELECT
indata[8] => temp6~16.OUTPUTSELECT
indata[8] => temp6~17.OUTPUTSELECT
indata[8] => temp6~18.OUTPUTSELECT
indata[8] => temp6~19.OUTPUTSELECT
indata[9] => temp5~32.OUTPUTSELECT
indata[9] => temp5~33.OUTPUTSELECT
indata[9] => temp5~34.OUTPUTSELECT
indata[9] => temp5~35.OUTPUTSELECT
indata[9] => temp6~25.OUTPUTSELECT
indata[9] => temp6~26.OUTPUTSELECT
indata[9] => temp6~27.OUTPUTSELECT
indata[9] => temp6~28.OUTPUTSELECT
indata[9] => temp6~29.OUTPUTSELECT
indata[10] => temp5~40.OUTPUTSELECT
indata[10] => temp5~41.OUTPUTSELECT
indata[10] => temp5~42.OUTPUTSELECT
indata[10] => temp5~43.OUTPUTSELECT
indata[10] => temp6~39.OUTPUTSELECT
indata[10] => temp6~40.OUTPUTSELECT
indata[10] => temp6~41.OUTPUTSELECT
indata[10] => temp6~42.OUTPUTSELECT
indata[10] => temp6~43.OUTPUTSELECT
clear => temp1[3].ACLR
clear => temp1[2].ACLR
clear => temp1[1].ACLR
clear => temp1[0].ACLR
clear => temp2[4].ACLR
clear => temp2[3].ACLR
clear => temp2[2].ACLR
clear => temp2[1].ACLR
clear => temp2[0].ACLR
clear => temp3[4].ACLR
clear => temp3[3].ACLR
clear => temp3[2].ACLR
clear => temp3[1].ACLR
clear => temp3[0].ACLR
clear => temp4[4].ACLR
clear => temp4[3].ACLR
clear => temp4[2].ACLR
clear => temp4[1].ACLR
clear => temp4[0].ACLR
clear => temp5[4].ACLR
clear => temp5[3].ACLR
clear => temp5[2].ACLR
clear => temp5[1].ACLR
clear => temp5[0].ACLR
clear => temp6[4].ACLR
clear => temp6[3].ACLR
clear => temp6[2].ACLR
clear => temp6[1].ACLR
clear => temp6[0].ACLR
clear => temp1[4].ACLR
clear => b1[3]~reg0.ENA
clear => b1[2]~reg0.ENA
clear => b1[1]~reg0.ENA
clear => b1[0]~reg0.ENA
clear => b2[3]~reg0.ENA
clear => b2[2]~reg0.ENA
clear => b2[1]~reg0.ENA
clear => b2[0]~reg0.ENA
clear => b3[3]~reg0.ENA
clear => b3[2]~reg0.ENA
clear => b3[1]~reg0.ENA
clear => b3[0]~reg0.ENA
clear => b4[3]~reg0.ENA
clear => b4[2]~reg0.ENA
clear => b4[1]~reg0.ENA
clear => b4[0]~reg0.ENA
clear => b5[3]~reg0.ENA
clear => b5[2]~reg0.ENA
clear => b5[1]~reg0.ENA
clear => b5[0]~reg0.ENA
clear => b6[3]~reg0.ENA
clear => b6[2]~reg0.ENA
clear => b6[1]~reg0.ENA
clear => b6[0]~reg0.ENA
enable => temp1[3].CLK
enable => temp1[2].CLK
enable => temp1[1].CLK
enable => temp1[0].CLK
enable => temp2[4].CLK
enable => temp2[3].CLK
enable => temp2[2].CLK
enable => temp2[1].CLK
enable => temp2[0].CLK
enable => temp3[4].CLK
enable => temp3[3].CLK
enable => temp3[2].CLK
enable => temp3[1].CLK
enable => temp3[0].CLK
enable => temp4[4].CLK
enable => temp4[3].CLK
enable => temp4[2].CLK
enable => temp4[1].CLK
enable => temp4[0].CLK
enable => temp5[4].CLK
enable => temp5[3].CLK
enable => temp5[2].CLK
enable => temp5[1].CLK
enable => temp5[0].CLK
enable => temp6[4].CLK
enable => temp6[3].CLK
enable => temp6[2].CLK
enable => temp6[1].CLK
enable => temp6[0].CLK
enable => b1[3]~reg0.CLK
enable => b1[2]~reg0.CLK
enable => b1[1]~reg0.CLK
enable => b1[0]~reg0.CLK
enable => b2[3]~reg0.CLK
enable => b2[2]~reg0.CLK
enable => b2[1]~reg0.CLK
enable => b2[0]~reg0.CLK
enable => b3[3]~reg0.CLK
enable => b3[2]~reg0.CLK
enable => b3[1]~reg0.CLK
enable => b3[0]~reg0.CLK
enable => b4[3]~reg0.CLK
enable => b4[2]~reg0.CLK
enable => b4[1]~reg0.CLK
enable => b4[0]~reg0.CLK
enable => b5[3]~reg0.CLK
enable => b5[2]~reg0.CLK
enable => b5[1]~reg0.CLK
enable => b5[0]~reg0.CLK
enable => b6[3]~reg0.CLK
enable => b6[2]~reg0.CLK
enable => b6[1]~reg0.CLK
enable => b6[0]~reg0.CLK
enable => temp1[4].CLK
b6[0] <= b6[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b6[1] <= b6[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b6[2] <= b6[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b6[3] <= b6[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b5[0] <= b5[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b5[1] <= b5[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b5[2] <= b5[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b5[3] <= b5[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b4[0] <= b4[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b4[1] <= b4[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b4[2] <= b4[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b4[3] <= b4[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b3[0] <= b3[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b3[1] <= b3[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b3[2] <= b3[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b3[3] <= b3[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b2[0] <= b2[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b2[1] <= b2[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b2[2] <= b2[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b2[3] <= b2[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b1[0] <= b1[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b1[1] <= b1[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b1[2] <= b1[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b1[3] <= b1[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE