system1.map.qmsg

用VHDL语言实现的控制DS18B20构成测温仪表的程序

{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|system1\|led_convertor:display_component\|fsm3 " "Info: Selected Auto state machine encoding method for state machine \"\|system1\|led_convertor:display_component\|fsm3\"" {  } { { "led_convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/led_convertor.vhd" 15 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|system1\|led_convertor:display_component\|fsm3 " "Info: Encoding result for state machine \"\|system1\|led_convertor:display_component\|fsm3\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "3 " "Info: Completed encoding using 3 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "led_convertor:display_component\|state_6 " "Info: Encoded state bit \"led_convertor:display_component\|state_6\"" {  } { { "led_convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/led_convertor.vhd" 87 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "led_convertor:display_component\|state_4 " "Info: Encoded state bit \"led_convertor:display_component\|state_4\"" {  } { { "led_convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/led_convertor.vhd" 87 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "led_convertor:display_component\|state_1 " "Info: Encoded state bit \"led_convertor:display_component\|state_1\"" {  } { { "led_convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/led_convertor.vhd" 87 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|system1\|led_convertor:display_component\|state_1 000 " "Info: State \"\|system1\|led_convertor:display_component\|state_1\" uses code string \"000\"" {  } { { "led_convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/led_convertor.vhd" 87 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|system1\|led_convertor:display_component\|state_4 011 " "Info: State \"\|system1\|led_convertor:display_component\|state_4\" uses code string \"011\"" {  } { { "led_convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/led_convertor.vhd" 87 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|system1\|led_convertor:display_component\|state_6 101 " "Info: State \"\|system1\|led_convertor:display_component\|state_6\" uses code string \"101\"" {  } { { "led_convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/led_convertor.vhd" 87 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "led_convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/led_convertor.vhd" 15 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|system1\|led_convertor:display_component\|state " "Info: Selected Auto state machine encoding method for state machine \"\|system1\|led_convertor:display_component\|state\"" {  } { { "led_convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/led_convertor.vhd" 15 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|system1\|led_convertor:display_component\|state " "Info: Encoding result for state machine \"\|system1\|led_convertor:display_component\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "3 " "Info: Completed encoding using 3 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "led_convertor:display_component\|state.display " "Info: Encoded state bit \"led_convertor:display_component\|state.display\"" {  } { { "led_convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/led_convertor.vhd" 64 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "led_convertor:display_component\|state.enable " "Info: Encoded state bit \"led_convertor:display_component\|state.enable\"" {  } { { "led_convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/led_convertor.vhd" 64 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "led_convertor:display_component\|state.clear " "Info: Encoded state bit \"led_convertor:display_component\|state.clear\"" {  } { { "led_convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/led_convertor.vhd" 64 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|system1\|led_convertor:display_component\|state.clear 000 " "Info: State \"\|system1\|led_convertor:display_component\|state.clear\" uses code string \"000\"" {  } { { "led_convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/led_convertor.vhd" 64 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|system1\|led_convertor:display_component\|state.enable 011 " "Info: State \"\|system1\|led_convertor:display_component\|state.enable\" uses code string \"011\"" {  } { { "led_convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/led_convertor.vhd" 64 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|system1\|led_convertor:display_component\|state.display 101 " "Info: State \"\|system1\|led_convertor:display_component\|state.display\" uses code string \"101\"" {  } { { "led_convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/led_convertor.vhd" 64 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "led_convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/led_convertor.vhd" 15 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "lpm_bustri:lpm_bustri_component\|din\[0\] " "Warning: Converting TRI node \"lpm_bustri:lpm_bustri_component\|din\[0\]\" that feeds logic to an OR gate" {  } { { "lpm_bustri.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "closedots\[0\] VCC " "Warning: Pin \"closedots\[0\]\" stuck at VCC" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "closedots\[1\] VCC " "Warning: Pin \"closedots\[1\]\" stuck at VCC" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "closedots\[2\] VCC " "Warning: Pin \"closedots\[2\]\" stuck at VCC" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "closedots\[3\] VCC " "Warning: Pin \"closedots\[3\]\" stuck at VCC" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "closedots\[4\] VCC " "Warning: Pin \"closedots\[4\]\" stuck at VCC" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "closedots\[5\] VCC " "Warning: Pin \"closedots\[5\]\" stuck at VCC" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "closedots\[6\] VCC " "Warning: Pin \"closedots\[6\]\" stuck at VCC" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "closedots\[7\] VCC " "Warning: Pin \"closedots\[7\]\" stuck at VCC" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "514 " "Info: Implemented 514 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "22 " "Info: Implemented 22 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_BIDIRS" "1 " "Info: Implemented 1 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "490 " "Info: Implemented 490 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 10 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 27 10:24:22 2006 " "Info: Processing ended: Fri Oct 27 10:24:22 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:43 " "Info: Elapsed time: 00:00:43" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}