system1.map.qmsg

用VHDL语言实现的控制DS18B20构成测温仪表的程序

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "convertor led_convertor:display_component\|convertor:my_convert " "Info: Elaborating entity \"convertor\" for hierarchy \"led_convertor:display_component\|convertor:my_convert\"" {  } { { "led_convertor.vhd" "my_convert" { Text "D:/altera/my vhdl file/system1/led_convertor.vhd" 40 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../quartus51/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../quartus51/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../quartus51/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../quartus51/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../quartus51/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../quartus51/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../quartus51/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../quartus51/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|system1\|allstate 24 " "Info: State machine \"\|system1\|allstate\" contains 24 states" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 24 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|system1\|led_convertor:display_component\|fsm3 3 " "Info: State machine \"\|system1\|led_convertor:display_component\|fsm3\" contains 3 states" {  } { { "led_convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/led_convertor.vhd" 15 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|system1\|led_convertor:display_component\|state 3 " "Info: State machine \"\|system1\|led_convertor:display_component\|state\" contains 3 states" {  } { { "led_convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/led_convertor.vhd" 15 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|system1\|allstate " "Info: Selected Auto state machine encoding method for state machine \"\|system1\|allstate\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 24 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|system1\|allstate " "Info: Encoding result for state machine \"\|system1\|allstate\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "24 " "Info: Completed encoding using 24 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "allstate.display " "Info: Encoded state bit \"allstate.display\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "allstate.rstop " "Info: Encoded state bit \"allstate.rstop\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "allstate.rwait_55u " "Info: Encoded state bit \"allstate.rwait_55u\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "allstate.rwait_9u " "Info: Encoded state bit \"allstate.rwait_9u\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "allstate.rwait_6u " "Info: Encoded state bit \"allstate.rwait_6u\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "allstate.rmaster " "Info: Encoded state bit \"allstate.rmaster\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "allstate.wstop2 " "Info: Encoded state bit \"allstate.wstop2\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "allstate.wait2_10u " "Info: Encoded state bit \"allstate.wait2_10u\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "allstate.write2_0 " "Info: Encoded state bit \"allstate.write2_0\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "allstate.wait2_64u " "Info: Encoded state bit \"allstate.wait2_64u\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "allstate.write2_1 " "Info: Encoded state bit \"allstate.write2_1\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "allstate.wmaster2 " "Info: Encoded state bit \"allstate.wmaster2\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "allstate.tempstay_750m " "Info: Encoded state bit \"allstate.tempstay_750m\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "allstate.wstop1 " "Info: Encoded state bit \"allstate.wstop1\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "allstate.wait1_10u " "Info: Encoded state bit \"allstate.wait1_10u\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "allstate.write1_0 " "Info: Encoded state bit \"allstate.write1_0\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "allstate.wait1_64u " "Info: Encoded state bit \"allstate.wait1_64u\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "allstate.write1_1 " "Info: Encoded state bit \"allstate.write1_1\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "allstate.wmaster1 " "Info: Encoded state bit \"allstate.wmaster1\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "allstate.reset_jump " "Info: Encoded state bit \"allstate.reset_jump\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "allstate.wait_410u " "Info: Encoded state bit \"allstate.wait_410u\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "allstate.wait_70u " "Info: Encoded state bit \"allstate.wait_70u\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "allstate.wait_480u " "Info: Encoded state bit \"allstate.wait_480u\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "allstate.resetstart " "Info: Encoded state bit \"allstate.resetstart\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|system1\|allstate.resetstart 000000000000000000000000 " "Info: State \"\|system1\|allstate.resetstart\" uses code string \"000000000000000000000000\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|system1\|allstate.wait_480u 000000000000000000000011 " "Info: State \"\|system1\|allstate.wait_480u\" uses code string \"000000000000000000000011\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|system1\|allstate.wait_70u 000000000000000000000101 " "Info: State \"\|system1\|allstate.wait_70u\" uses code string \"000000000000000000000101\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|system1\|allstate.wait_410u 000000000000000000001001 " "Info: State \"\|system1\|allstate.wait_410u\" uses code string \"000000000000000000001001\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|system1\|allstate.reset_jump 000000000000000000010001 " "Info: State \"\|system1\|allstate.reset_jump\" uses code string \"000000000000000000010001\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|system1\|allstate.wmaster1 000000000000000000100001 " "Info: State \"\|system1\|allstate.wmaster1\" uses code string \"000000000000000000100001\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|system1\|allstate.write1_1 000000000000000001000001 " "Info: State \"\|system1\|allstate.write1_1\" uses code string \"000000000000000001000001\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|system1\|allstate.wait1_64u 000000000000000010000001 " "Info: State \"\|system1\|allstate.wait1_64u\" uses code string \"000000000000000010000001\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|system1\|allstate.write1_0 000000000000000100000001 " "Info: State \"\|system1\|allstate.write1_0\" uses code string \"000000000000000100000001\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|system1\|allstate.wait1_10u 000000000000001000000001 " "Info: State \"\|system1\|allstate.wait1_10u\" uses code string \"000000000000001000000001\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|system1\|allstate.wstop1 000000000000010000000001 " "Info: State \"\|system1\|allstate.wstop1\" uses code string \"000000000000010000000001\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|system1\|allstate.tempstay_750m 000000000000100000000001 " "Info: State \"\|system1\|allstate.tempstay_750m\" uses code string \"000000000000100000000001\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|system1\|allstate.wmaster2 000000000001000000000001 " "Info: State \"\|system1\|allstate.wmaster2\" uses code string \"000000000001000000000001\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|system1\|allstate.write2_1 000000000010000000000001 " "Info: State \"\|system1\|allstate.write2_1\" uses code string \"000000000010000000000001\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|system1\|allstate.wait2_64u 000000000100000000000001 " "Info: State \"\|system1\|allstate.wait2_64u\" uses code string \"000000000100000000000001\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|system1\|allstate.write2_0 000000001000000000000001 " "Info: State \"\|system1\|allstate.write2_0\" uses code string \"000000001000000000000001\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|system1\|allstate.wait2_10u 000000010000000000000001 " "Info: State \"\|system1\|allstate.wait2_10u\" uses code string \"000000010000000000000001\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|system1\|allstate.wstop2 000000100000000000000001 " "Info: State \"\|system1\|allstate.wstop2\" uses code string \"000000100000000000000001\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|system1\|allstate.rmaster 000001000000000000000001 " "Info: State \"\|system1\|allstate.rmaster\" uses code string \"000001000000000000000001\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|system1\|allstate.rwait_6u 000010000000000000000001 " "Info: State \"\|system1\|allstate.rwait_6u\" uses code string \"000010000000000000000001\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|system1\|allstate.rwait_9u 000100000000000000000001 " "Info: State \"\|system1\|allstate.rwait_9u\" uses code string \"000100000000000000000001\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|system1\|allstate.rwait_55u 001000000000000000000001 " "Info: State \"\|system1\|allstate.rwait_55u\" uses code string \"001000000000000000000001\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|system1\|allstate.rstop 010000000000000000000001 " "Info: State \"\|system1\|allstate.rstop\" uses code string \"010000000000000000000001\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|system1\|allstate.display 100000000000000000000001 " "Info: State \"\|system1\|allstate.display\" uses code string \"100000000000000000000001\"" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 24 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}