system1.tan.qmsg

用VHDL语言实现的控制DS18B20构成测温仪表的程序

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "ramdata\[4\] led_convertor:display_component\|convertor:my_convert\|temp4\[3\] clock 7.1 ns " "Info: Found hold time violation between source  pin or register \"ramdata\[4\]\" and destination pin or register \"led_convertor:display_component\|convertor:my_convert\|temp4\[3\]\" for clock \"clock\" (Hold time is 7.1 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "10.400 ns + Largest " "Info: + Largest clock skew is 10.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 21.400 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 21.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clock 1 CLK PIN_43 5 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 5; CLK Node = 'clock'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "" { clock } "NODE_NAME" } "" } } { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns clk_1u 2 REG LC1_A12 84 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_A12; Fanout = 84; REG Node = 'clk_1u'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "3.600 ns" { clock clk_1u } "NODE_NAME" } "" } } { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.600 ns) + CELL(1.100 ns) 12.100 ns led_convertor:display_component\|clk_1k 3 REG LC1_A21 30 " "Info: 3: + IC(4.600 ns) + CELL(1.100 ns) = 12.100 ns; Loc. = LC1_A21; Fanout = 30; REG Node = 'led_convertor:display_component\|clk_1k'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "5.700 ns" { clk_1u led_convertor:display_component|clk_1k } "NODE_NAME" } "" } } { "led_convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/led_convertor.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(1.100 ns) 16.500 ns led_convertor:display_component\|enb 4 REG LC8_A13 54 " "Info: 4: + IC(3.300 ns) + CELL(1.100 ns) = 16.500 ns; Loc. = LC8_A13; Fanout = 54; REG Node = 'led_convertor:display_component\|enb'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "4.400 ns" { led_convertor:display_component|clk_1k led_convertor:display_component|enb } "NODE_NAME" } "" } } { "led_convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/led_convertor.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.900 ns) + CELL(0.000 ns) 21.400 ns led_convertor:display_component\|convertor:my_convert\|temp4\[3\] 5 REG LC6_B2 2 " "Info: 5: + IC(4.900 ns) + CELL(0.000 ns) = 21.400 ns; Loc. = LC6_B2; Fanout = 2; REG Node = 'led_convertor:display_component\|convertor:my_convert\|temp4\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "4.900 ns" { led_convertor:display_component|enb led_convertor:display_component|convertor:my_convert|temp4[3] } "NODE_NAME" } "" } } { "convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/convertor.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.100 ns ( 28.50 % ) " "Info: Total cell delay = 6.100 ns ( 28.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "15.300 ns ( 71.50 % ) " "Info: Total interconnect delay = 15.300 ns ( 71.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "21.400 ns" { clock clk_1u led_convertor:display_component|clk_1k led_convertor:display_component|enb led_convertor:display_component|convertor:my_convert|temp4[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "21.400 ns" { clock clock~out clk_1u led_convertor:display_component|clk_1k led_convertor:display_component|enb led_convertor:display_component|convertor:my_convert|temp4[3] } { 0.000ns 0.000ns 2.500ns 4.600ns 3.300ns 4.900ns } { 0.000ns 2.800ns 1.100ns 1.100ns 1.100ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 11.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to source register is 11.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clock 1 CLK PIN_43 5 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 5; CLK Node = 'clock'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "" { clock } "NODE_NAME" } "" } } { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns clk_1u 2 REG LC1_A12 84 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_A12; Fanout = 84; REG Node = 'clk_1u'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "3.600 ns" { clock clk_1u } "NODE_NAME" } "" } } { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.600 ns) + CELL(0.000 ns) 11.000 ns ramdata\[4\] 3 REG LC6_B1 8 " "Info: 3: + IC(4.600 ns) + CELL(0.000 ns) = 11.000 ns; Loc. = LC6_B1; Fanout = 8; REG Node = 'ramdata\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "4.600 ns" { clk_1u ramdata[4] } "NODE_NAME" } "" } } { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns ( 35.45 % ) " "Info: Total cell delay = 3.900 ns ( 35.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.100 ns ( 64.55 % ) " "Info: Total interconnect delay = 7.100 ns ( 64.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "11.000 ns" { clock clk_1u ramdata[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.000 ns" { clock clock~out clk_1u ramdata[4] } { 0.000ns 0.000ns 2.500ns 4.600ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "21.400 ns" { clock clk_1u led_convertor:display_component|clk_1k led_convertor:display_component|enb led_convertor:display_component|convertor:my_convert|temp4[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "21.400 ns" { clock clock~out clk_1u led_convertor:display_component|clk_1k led_convertor:display_component|enb led_convertor:display_component|convertor:my_convert|temp4[3] } { 0.000ns 0.000ns 2.500ns 4.600ns 3.300ns 4.900ns } { 0.000ns 2.800ns 1.100ns 1.100ns 1.100ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "11.000 ns" { clock clk_1u ramdata[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.000 ns" { clock clock~out clk_1u ramdata[4] } { 0.000ns 0.000ns 2.500ns 4.600ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns - " "Info: - Micro clock to output delay of source is 1.100 ns" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.800 ns - Shortest register register " "Info: - Shortest register to register delay is 3.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ramdata\[4\] 1 REG LC6_B1 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_B1; Fanout = 8; REG Node = 'ramdata\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "" { ramdata[4] } "NODE_NAME" } "" } } { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 109 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(1.200 ns) 3.800 ns led_convertor:display_component\|convertor:my_convert\|temp4\[3\] 2 REG LC6_B2 2 " "Info: 2: + IC(2.600 ns) + CELL(1.200 ns) = 3.800 ns; Loc. = LC6_B2; Fanout = 2; REG Node = 'led_convertor:display_component\|convertor:my_convert\|temp4\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "3.800 ns" { ramdata[4] led_convertor:display_component|convertor:my_convert|temp4[3] } "NODE_NAME" } "" } } { "convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/convertor.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.200 ns ( 31.58 % ) " "Info: Total cell delay = 1.200 ns ( 31.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns ( 68.42 % ) " "Info: Total interconnect delay = 2.600 ns ( 68.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "3.800 ns" { ramdata[4] led_convertor:display_component|convertor:my_convert|temp4[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.800 ns" { ramdata[4] led_convertor:display_component|convertor:my_convert|temp4[3] } { 0.000ns 2.600ns } { 0.000ns 1.200ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" {  } { { "convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/convertor.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "21.400 ns" { clock clk_1u led_convertor:display_component|clk_1k led_convertor:display_component|enb led_convertor:display_component|convertor:my_convert|temp4[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "21.400 ns" { clock clock~out clk_1u led_convertor:display_component|clk_1k led_convertor:display_component|enb led_convertor:display_component|convertor:my_convert|temp4[3] } { 0.000ns 0.000ns 2.500ns 4.600ns 3.300ns 4.900ns } { 0.000ns 2.800ns 1.100ns 1.100ns 1.100ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "11.000 ns" { clock clk_1u ramdata[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.000 ns" { clock clock~out clk_1u ramdata[4] } { 0.000ns 0.000ns 2.500ns 4.600ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "3.800 ns" { ramdata[4] led_convertor:display_component|convertor:my_convert|temp4[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.800 ns" { ramdata[4] led_convertor:display_component|convertor:my_convert|temp4[3] } { 0.000ns 2.600ns } { 0.000ns 1.200ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "\\Reset1:present dq\[0\] clock 2.800 ns register " "Info: tsu for register \"\\Reset1:present\" (data pin = \"dq\[0\]\", clock pin = \"clock\") is 2.800 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.300 ns + Longest pin register " "Info: + Longest pin to register delay is 11.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dq\[0\] 1 PIN PIN_35 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_35; Fanout = 1; PIN Node = 'dq\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "" { dq[0] } "NODE_NAME" } "" } } { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns dq\[0\]~0 2 COMB IOC_35 12 " "Info: 2: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = IOC_35; Fanout = 12; COMB Node = 'dq\[0\]~0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "3.500 ns" { dq[0] dq[0]~0 } "NODE_NAME" } "" } } { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(2.300 ns) 9.000 ns Select~5539 3 COMB LC8_C6 1 " "Info: 3: + IC(3.200 ns) + CELL(2.300 ns) = 9.000 ns; Loc. = LC8_C6; Fanout = 1; COMB Node = 'Select~5539'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "5.500 ns" { dq[0]~0 Select~5539 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.700 ns) 11.300 ns \\Reset1:present 4 REG LC6_C6 4 " "Info: 4: + IC(0.600 ns) + CELL(1.700 ns) = 11.300 ns; Loc. = LC6_C6; Fanout = 4; REG Node = '\\Reset1:present'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "2.300 ns" { Select~5539 \Reset1:present } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.500 ns ( 66.37 % ) " "Info: Total cell delay = 7.500 ns ( 66.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.800 ns ( 33.63 % ) " "Info: Total interconnect delay = 3.800 ns ( 33.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "11.300 ns" { dq[