📄 system1.tan.qmsg
字号:
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "led_convertor:display_component\|enb " "Info: Detected ripple clock \"led_convertor:display_component\|enb\" as buffer" { } { { "led_convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/led_convertor.vhd" 26 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "led_convertor:display_component\|enb" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clk_1u " "Info: Detected ripple clock \"clk_1u\" as buffer" { } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 16 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk_1u" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "led_convertor:display_component\|clk_1k " "Info: Detected ripple clock \"led_convertor:display_component\|clk_1k\" as buffer" { } { { "led_convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/led_convertor.vhd" 18 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "led_convertor:display_component\|clk_1k" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register led_convertor:display_component\|convertor:my_convert\|temp5\[0\] register led_convertor:display_component\|convertor:my_convert\|b6\[1\] 15.38 MHz 65.0 ns Internal " "Info: Clock \"clock\" has Internal fmax of 15.38 MHz between source register \"led_convertor:display_component\|convertor:my_convert\|temp5\[0\]\" and destination register \"led_convertor:display_component\|convertor:my_convert\|b6\[1\]\" (period= 65.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "60.500 ns + Longest register register " "Info: + Longest register to register delay is 60.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns led_convertor:display_component\|convertor:my_convert\|temp5\[0\] 1 REG LC2_B7 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_B7; Fanout = 6; REG Node = 'led_convertor:display_component\|convertor:my_convert\|temp5\[0\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "" { led_convertor:display_component|convertor:my_convert|temp5[0] } "NODE_NAME" } "" } } { "convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/convertor.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.800 ns) 4.000 ns led_convertor:display_component\|convertor:my_convert\|add~2384 2 COMB LC5_B8 2 " "Info: 2: + IC(2.200 ns) + CELL(1.800 ns) = 4.000 ns; Loc. = LC5_B8; Fanout = 2; COMB Node = 'led_convertor:display_component\|convertor:my_convert\|add~2384'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "4.000 ns" { led_convertor:display_component|convertor:my_convert|temp5[0] led_convertor:display_component|convertor:my_convert|add~2384 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 6.900 ns led_convertor:display_component\|convertor:my_convert\|add~2385 3 COMB LC1_B8 2 " "Info: 3: + IC(0.600 ns) + CELL(2.300 ns) = 6.900 ns; Loc. = LC1_B8; Fanout = 2; COMB Node = 'led_convertor:display_component\|convertor:my_convert\|add~2385'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "2.900 ns" { led_convertor:display_component|convertor:my_convert|add~2384 led_convertor:display_component|convertor:my_convert|add~2385 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 11.400 ns led_convertor:display_component\|convertor:my_convert\|add~2386 4 COMB LC7_B9 5 " "Info: 4: + IC(2.200 ns) + CELL(2.300 ns) = 11.400 ns; Loc. = LC7_B9; Fanout = 5; COMB Node = 'led_convertor:display_component\|convertor:my_convert\|add~2386'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "4.500 ns" { led_convertor:display_component|convertor:my_convert|add~2385 led_convertor:display_component|convertor:my_convert|add~2386 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 14.300 ns led_convertor:display_component\|convertor:my_convert\|LessThan~478 5 COMB LC1_B9 5 " "Info: 5: + IC(0.600 ns) + CELL(2.300 ns) = 14.300 ns; Loc. = LC1_B9; Fanout = 5; COMB Node = 'led_convertor:display_component\|convertor:my_convert\|LessThan~478'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "2.900 ns" { led_convertor:display_component|convertor:my_convert|add~2386 led_convertor:display_component|convertor:my_convert|LessThan~478 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(1.800 ns) 18.500 ns led_convertor:display_component\|convertor:my_convert\|temp5~1318 6 COMB LC4_B11 7 " "Info: 6: + IC(2.400 ns) + CELL(1.800 ns) = 18.500 ns; Loc. = LC4_B11; Fanout = 7; COMB Node = 'led_convertor:display_component\|convertor:my_convert\|temp5~1318'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "4.200 ns" { led_convertor:display_component|convertor:my_convert|LessThan~478 led_convertor:display_component|convertor:my_convert|temp5~1318 } "NODE_NAME" } "" } } { "convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/convertor.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 23.000 ns led_convertor:display_component\|convertor:my_convert\|LessThan~479 7 COMB LC6_B10 5 " "Info: 7: + IC(2.200 ns) + CELL(2.300 ns) = 23.000 ns; Loc. = LC6_B10; Fanout = 5; COMB Node = 'led_convertor:display_component\|convertor:my_convert\|LessThan~479'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "4.500 ns" { led_convertor:display_component|convertor:my_convert|temp5~1318 led_convertor:display_component|convertor:my_convert|LessThan~479 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 25.400 ns led_convertor:display_component\|convertor:my_convert\|temp5~1325 8 COMB LC1_B10 1 " "Info: 8: + IC(0.600 ns) + CELL(1.800 ns) = 25.400 ns; Loc. = LC1_B10; Fanout = 1; COMB Node = 'led_convertor:display_component\|convertor:my_convert\|temp5~1325'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "2.400 ns" { led_convertor:display_component|convertor:my_convert|LessThan~479 led_convertor:display_component|convertor:my_convert|temp5~1325 } "NODE_NAME" } "" } } { "convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/convertor.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 28.300 ns led_convertor:display_component\|convertor:my_convert\|temp5~1326 9 COMB LC7_B10 4 " "Info: 9: + IC(0.600 ns) + CELL(2.300 ns) = 28.300 ns; Loc. = LC7_B10; Fanout = 4; COMB Node = 'led_convertor:display_component\|convertor:my_convert\|temp5~1326'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "2.900 ns" { led_convertor:display_component|convertor:my_convert|temp5~1325 led_convertor:display_component|convertor:my_convert|temp5~1326 } "NODE_NAME" } "" } } { "convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/convertor.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(2.300 ns) 33.000 ns led_convertor:display_component\|convertor:my_convert\|LessThan~482 10 COMB LC8_B12 4 " "Info: 10: + IC(2.400 ns) + CELL(2.300 ns) = 33.000 ns; Loc. = LC8_B12; Fanout = 4; COMB Node = 'led_convertor:display_component\|convertor:my_convert\|LessThan~482'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "4.700 ns" { led_convertor:display_component|convertor:my_convert|temp5~1326 led_convertor:display_component|convertor:my_convert|LessThan~482 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(1.200 ns) 36.900 ns led_convertor:display_component\|convertor:my_convert\|lpm_add_sub:add_rtl_10\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\] 11 COMB LC3_B17 2 " "Info: 11: + IC(2.700 ns) + CELL(1.200 ns) = 36.900 ns; Loc. = LC3_B17; Fanout = 2; COMB Node = 'led_convertor:display_component\|convertor:my_convert\|lpm_add_sub:add_rtl_10\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "3.900 ns" { led_convertor:display_component|convertor:my_convert|LessThan~482 led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_10|addcore:adder|a_csnbuffer:result_node|cout[0] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 37.200 ns led_convertor:display_component\|convertor:my_convert\|lpm_add_sub:add_rtl_10\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\] 12 COMB LC4_B17 2 " "Info: 12: + IC(0.000 ns) + CELL(0.300 ns) = 37.200 ns; Loc. = LC4_B17; Fanout = 2; COMB Node = 'led_convertor:display_component\|convertor:my_convert\|lpm_add_sub:add_rtl_10\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "0.300 ns" { led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_10|addcore:adder|a_csnbuffer:result_node|cout[0] led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_10|addcore:adder|a_csnbuffer:result_node|cout[1] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 37.500 ns led_convertor:display_component\|convertor:my_convert\|lpm_add_sub:add_rtl_10\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\] 13 COMB LC5_B17 2 " "Info: 13: + IC(0.000 ns) + CELL(0.300 ns) = 37.500 ns; Loc. = LC5_B17; Fanout = 2; COMB Node = 'led_convertor:display_component\|convertor:my_convert\|lpm_add_sub:add_rtl_10\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "0.300 ns" { led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_10|addcore:adder|a_csnbuffer:result_node|cout[1] led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_10|addcore:adder|a_csnbuffer:result_node|cout[2] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 38.800 ns led_convertor:display_component\|convertor:my_convert\|lpm_add_sub:add_rtl_10\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\] 14 COMB LC6_B17 1 " "Info: 14: + IC(0.000 ns) + CELL(1.300 ns) = 38.800 ns; Loc. = LC6_B17; Fanout = 1; COMB Node = 'led_convertor:display_component\|convertor:my_convert\|lpm_add_sub:add_rtl_10\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "1.300 ns" { led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_10|addcore:adder|a_csnbuffer:result_node|cout[2] led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_10|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(2.300 ns) 43.200 ns led_convertor:display_component\|convertor:my_convert\|temp6~1463 15 COMB LC8_B16 5 " "Info: 15: + IC(2.100 ns) + CELL(2.300 ns) = 43.200 ns; Loc. = LC8_B16; Fanout = 5; COMB Node = 'led_convertor:display_component\|convertor:my_convert\|temp6~1463'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "4.400 ns" { led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_10|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] led_convertor:display_component|convertor:my_convert|temp6~1463 } "NODE_NAME" } "" } } { "convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/convertor.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(1.800 ns) 47.300 ns led_convertor:display_component\|convertor:my_convert\|add~2406 16 COMB LC2_B13 3 " "Info: 16: + IC(2.300 ns) + CELL(1.800 ns) = 47.300 ns; Loc. = LC2_B13; Fanout = 3; COMB Node = 'led_convertor:display_component\|convertor:my_convert\|add~2406'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "4.100 ns" { led_convertor:display_component|convertor:my_convert|temp6~1463 led_convertor:display_component|convertor:my_convert|add~2406 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 51.800 ns led_convertor:display_component\|convertor:my_convert\|lpm_add_sub:add_rtl_11\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\] 17 COMB LC5_B14 4 " "Info: 17: + IC(2.200 ns) + CELL(2.300 ns) = 51.800 ns; Loc. = LC5_B14; Fanout = 4; COMB Node = 'led_convertor:display_component\|convertor:my_convert\|lpm_add_sub:add_rtl_11\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "4.500 ns" { led_convertor:display_component|convertor:my_convert|add~2406 led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_11|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 56.300 ns led_convertor:display_component\|convertor:my_convert\|LessThan~477 18 COMB LC3_B13 3 " "Info: 18: + IC(2.200 ns) + CELL(2.300 ns) = 56.300 ns; Loc. = LC3_B13; Fanout = 3; COMB Node = 'led_convertor:display_component\|convertor:my_convert\|LessThan~477'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "4.500 ns" { led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_11|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] led_convertor:display_component|convertor:my_convert|LessThan~477 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 58.700 ns led_convertor:display_component\|convertor:my_convert\|temp6~1459 19 COMB LC6_B13 1 " "Info: 19: + IC(0.600 ns) + CELL(1.800 ns) = 58.700 ns; Loc. = LC6_B13; Fanout = 1; COMB Node = 'led_convertor:display_component\|convertor:my_convert\|temp6~1459'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "2.400 ns" { led_convertor:display_component|convertor:my_convert|LessThan~477 led_convertor:display_component|convertor:my_convert|temp6~1459 } "NODE_NAME" } "" } } { "convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/convertor.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.200 ns) 60.500 ns led_convertor:display_component\|convertor:my_convert\|b6\[1\] 20 REG LC4_B13 1 " "Info: 20: + IC(0.600 ns) + CELL(1.200 ns) = 60.500 ns; Loc. = LC4_B13; Fanout = 1; REG Node = 'led_convertor:display_component\|convertor:my_convert\|b6\[1\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "1.800 ns" { led_convertor:display_component|convertor:my_convert|temp6~1459 led_convertor:display_component|convertor:my_convert|b6[1] } "NODE_NAME" } "" } } { "convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/convertor.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "34.000 ns ( 56.20 % ) " "Info: Total cell delay = 34.000 ns ( 56.20 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "26.500 ns ( 43.80 % ) " "Info: Total interconnect delay = 26.500 ns ( 43.80 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "60.500 ns" { led_convertor:display_component|convertor:my_convert|temp5[0] led_convertor:display_component|convertor:my_convert|add~2384 led_convertor:display_component|convertor:my_convert|add~2385 led_convertor:display_component|convertor:my_convert|add~2386 led_convertor:display_component|convertor:my_convert|LessThan~478 led_convertor:display_component|convertor:my_convert|temp5~1318 led_convertor:display_component|convertor:my_convert|LessThan~479 led_convertor:display_component|convertor:my_convert|temp5~1325 led_convertor:display_component|convertor:my_convert|temp5~1326 led_convertor:display_component|convertor:my_convert|LessThan~482 led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_10|addcore:adder|a_csnbuffer:result_node|cout[0] led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_10|addcore:adder|a_csnbuffer:result_node|cout[1] led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_10|addcore:adder|a_csnbuffer:result_node|cout[2] led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_10|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] led_convertor:display_component|convertor:my_convert|temp6~1463 led_convertor:display_component|convertor:my_convert|add~2406 led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_11|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] led_convertor:display_component|convertor:my_convert|LessThan~477 led_convertor:display_component|convertor:my_convert|temp6~1459 led_convertor:display_component|convertor:my_convert|b6[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "60.500 ns" { led_convertor:display_component|convertor:my_convert|temp5[0] led_convertor:display_component|convertor:my_convert|add~2384 led_convertor:display_component|convertor:my_convert|add~2385 led_convertor:display_component|convertor:my_convert|add~2386 led_convertor:display_component|convertor:my_convert|LessThan~478 led_convertor:display_component|convertor:my_convert|temp5~1318 led_convertor:display_component|convertor:my_convert|LessThan~479 led_convertor:display_component|convertor:my_convert|temp5~1325 led_convertor:display_component|convertor:my_convert|temp5~1326 led_convertor:display_component|convertor:my_convert|LessThan~482 led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_10|addcore:adder|a_csnbuffer:result_node|cout[0] led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_10|addcore:adder|a_csnbuffer:result_node|cout[1] led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_10|addcore:adder|a_csnbuffer:result_node|cout[2] led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_10|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] led_convertor:display_component|convertor:my_convert|temp6~1463 led_convertor:display_component|convertor:my_convert|add~2406 led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_11|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] led_convertor:display_component|convertor:my_convert|LessThan~477 led_convertor:display_component|convertor:my_convert|temp6~1459 led_convertor:display_component|convertor:my_convert|b6[1] } { 0.000ns 2.200ns 0.600ns 2.200ns 0.600ns 2.400ns 2.200ns 0.600ns 0.600ns 2.400ns 2.700ns 0.000ns 0.000ns 0.000ns 2.100ns 2.300ns 2.200ns 2.200ns 0.600ns 0.600ns } { 0.000ns 1.800ns 2.300ns 2.300ns 2.300ns 1.800ns 2.300ns 1.800ns 2.300ns 2.300ns 1.200ns 0.300ns 0.300ns 1.300ns 2.300ns 1.800ns 2.300ns 2.300ns 1.800ns 1.200ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.900 ns - Smallest " "Info: - Smallest clock skew is -0.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 20.400 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 20.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clock 1 CLK PIN_43 5 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 5; CLK Node = 'clock'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "" { clock } "NODE_NAME" } "" } } { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns clk_1u 2 REG LC1_A12 84 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_A12; Fanout = 84; REG Node = 'clk_1u'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "3.600 ns" { clock clk_1u } "NODE_NAME" } "" } } { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.600 ns) + CELL(1.100 ns) 12.100 ns led_convertor:display_component\|clk_1k 3 REG LC1_A21 30 " "Info: 3: + IC(4.600 ns) + CELL(1.100 ns) = 12.100 ns; Loc. = LC1_A21; Fanout = 30; REG Node = 'led_convertor:display_component\|clk_1k'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "5.700 ns" { clk_1u led_convertor:display_component|clk_1k } "NODE_NAME" } "" } } { "led_convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/led_convertor.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(1.100 ns) 16.500 ns led_convertor:display_component\|enb 4 REG LC8_A13 54 " "Info: 4: + IC(3.300 ns) + CELL(1.100 ns) = 16.500 ns; Loc. = LC8_A13; Fanout = 54; REG Node = 'led_convertor:display_component\|enb'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "4.400 ns" { led_convertor:display_component|clk_1k led_convertor:display_component|enb } "NODE_NAME" } "" } } { "led_convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/led_convertor.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.900 ns) + CELL(0.000 ns) 20.400 ns led_convertor:display_component\|convertor:my_convert\|b6\[1\] 5 REG LC4_B13 1 " "Info: 5: + IC(3.900 ns) + CELL(0.000 ns) = 20.400 ns; Loc. = LC4_B13; Fanout = 1; REG Node = 'led_convertor:display_component\|convertor:my_convert\|b6\[1\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "3.900 ns" { led_convertor:display_component|enb led_convertor:display_component|convertor:my_convert|b6[1] } "NODE_NAME" } "" } } { "convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/convertor.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.100 ns ( 29.90 % ) " "Info: Total cell delay = 6.100 ns ( 29.90 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "14.300 ns ( 70.10 % ) " "Info: Total interconnect delay = 14.300 ns ( 70.10 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "20.400 ns" { clock clk_1u led_convertor:display_component|clk_1k led_convertor:display_component|enb led_convertor:display_component|convertor:my_convert|b6[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "20.400 ns" { clock clock~out clk_1u led_convertor:display_component|clk_1k led_convertor:display_component|enb led_convertor:display_component|convertor:my_convert|b6[1] } { 0.000ns 0.000ns 2.500ns 4.600ns 3.300ns 3.900ns } { 0.000ns 2.800ns 1.100ns 1.100ns 1.100ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 21.300 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 21.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clock 1 CLK PIN_43 5 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 5; CLK Node = 'clock'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "" { clock } "NODE_NAME" } "" } } { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns clk_1u 2 REG LC1_A12 84 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_A12; Fanout = 84; REG Node = 'clk_1u'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "3.600 ns" { clock clk_1u } "NODE_NAME" } "" } } { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.600 ns) + CELL(1.100 ns) 12.100 ns led_convertor:display_component\|clk_1k 3 REG LC1_A21 30 " "Info: 3: + IC(4.600 ns) + CELL(1.100 ns) = 12.100 ns; Loc. = LC1_A21; Fanout = 30; REG Node = 'led_convertor:display_component\|clk_1k'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "5.700 ns" { clk_1u led_convertor:display_component|clk_1k } "NODE_NAME" } "" } } { "led_convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/led_convertor.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(1.100 ns) 16.500 ns led_convertor:display_component\|enb 4 REG LC8_A13 54 " "Info: 4: + IC(3.300 ns) + CELL(1.100 ns) = 16.500 ns; Loc. = LC8_A13; Fanout = 54; REG Node = 'led_convertor:display_component\|enb'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "4.400 ns" { led_convertor:display_component|clk_1k led_convertor:display_component|enb } "NODE_NAME" } "" } } { "led_convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/led_convertor.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.800 ns) + CELL(0.000 ns) 21.300 ns led_convertor:display_component\|convertor:my_convert\|temp5\[0\] 5 REG LC2_B7 6 " "Info: 5: + IC(4.800 ns) + CELL(0.000 ns) = 21.300 ns; Loc. = LC2_B7; Fanout = 6; REG Node = 'led_convertor:display_component\|convertor:my_convert\|temp5\[0\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "4.800 ns" { led_convertor:display_component|enb led_convertor:display_component|convertor:my_convert|temp5[0] } "NODE_NAME" } "" } } { "convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/convertor.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.100 ns ( 28.64 % ) " "Info: Total cell delay = 6.100 ns ( 28.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "15.200 ns ( 71.36 % ) " "Info: Total interconnect delay = 15.200 ns ( 71.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "21.300 ns" { clock clk_1u led_convertor:display_component|clk_1k led_convertor:display_component|enb led_convertor:display_component|convertor:my_convert|temp5[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "21.300 ns" { clock clock~out clk_1u led_convertor:display_component|clk_1k led_convertor:display_component|enb led_convertor:display_component|convertor:my_convert|temp5[0] } { 0.000ns 0.000ns 2.500ns 4.600ns 3.300ns 4.800ns } { 0.000ns 2.800ns 1.100ns 1.100ns 1.100ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "20.400 ns" { clock clk_1u led_convertor:display_component|clk_1k led_convertor:display_component|enb led_convertor:display_component|convertor:my_convert|b6[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "20.400 ns" { clock clock~out clk_1u led_convertor:display_component|clk_1k led_convertor:display_component|enb led_convertor:display_component|convertor:my_convert|b6[1] } { 0.000ns 0.000ns 2.500ns 4.600ns 3.300ns 3.900ns } { 0.000ns 2.800ns 1.100ns 1.100ns 1.100ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "21.300 ns" { clock clk_1u led_convertor:display_component|clk_1k led_convertor:display_component|enb led_convertor:display_component|convertor:my_convert|temp5[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "21.300 ns" { clock clock~out clk_1u led_convertor:display_component|clk_1k led_convertor:display_component|enb led_convertor:display_component|convertor:my_convert|temp5[0] } { 0.000ns 0.000ns 2.500ns 4.600ns 3.300ns 4.800ns } { 0.000ns 2.800ns 1.100ns 1.100ns 1.100ns 0.000ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" { } { { "convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/convertor.vhd" 20 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" { } { { "convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/convertor.vhd" 20 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "60.500 ns" { led_convertor:display_component|convertor:my_convert|temp5[0] led_convertor:display_component|convertor:my_convert|add~2384 led_convertor:display_component|convertor:my_convert|add~2385 led_convertor:display_component|convertor:my_convert|add~2386 led_convertor:display_component|convertor:my_convert|LessThan~478 led_convertor:display_component|convertor:my_convert|temp5~1318 led_convertor:display_component|convertor:my_convert|LessThan~479 led_convertor:display_component|convertor:my_convert|temp5~1325 led_convertor:display_component|convertor:my_convert|temp5~1326 led_convertor:display_component|convertor:my_convert|LessThan~482 led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_10|addcore:adder|a_csnbuffer:result_node|cout[0] led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_10|addcore:adder|a_csnbuffer:result_node|cout[1] led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_10|addcore:adder|a_csnbuffer:result_node|cout[2] led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_10|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] led_convertor:display_component|convertor:my_convert|temp6~1463 led_convertor:display_component|convertor:my_convert|add~2406 led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_11|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] led_convertor:display_component|convertor:my_convert|LessThan~477 led_convertor:display_component|convertor:my_convert|temp6~1459 led_convertor:display_component|convertor:my_convert|b6[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "60.500 ns" { led_convertor:display_component|convertor:my_convert|temp5[0] led_convertor:display_component|convertor:my_convert|add~2384 led_convertor:display_component|convertor:my_convert|add~2385 led_convertor:display_component|convertor:my_convert|add~2386 led_convertor:display_component|convertor:my_convert|LessThan~478 led_convertor:display_component|convertor:my_convert|temp5~1318 led_convertor:display_component|convertor:my_convert|LessThan~479 led_convertor:display_component|convertor:my_convert|temp5~1325 led_convertor:display_component|convertor:my_convert|temp5~1326 led_convertor:display_component|convertor:my_convert|LessThan~482 led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_10|addcore:adder|a_csnbuffer:result_node|cout[0] led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_10|addcore:adder|a_csnbuffer:result_node|cout[1] led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_10|addcore:adder|a_csnbuffer:result_node|cout[2] led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_10|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] led_convertor:display_component|convertor:my_convert|temp6~1463 led_convertor:display_component|convertor:my_convert|add~2406 led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_11|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] led_convertor:display_component|convertor:my_convert|LessThan~477 led_convertor:display_component|convertor:my_convert|temp6~1459 led_convertor:display_component|convertor:my_convert|b6[1] } { 0.000ns 2.200ns 0.600ns 2.200ns 0.600ns 2.400ns 2.200ns 0.600ns 0.600ns 2.400ns 2.700ns 0.000ns 0.000ns 0.000ns 2.100ns 2.300ns 2.200ns 2.200ns 0.600ns 0.600ns } { 0.000ns 1.800ns 2.300ns 2.300ns 2.300ns 1.800ns 2.300ns 1.800ns 2.300ns 2.300ns 1.200ns 0.300ns 0.300ns 1.300ns 2.300ns 1.800ns 2.300ns 2.300ns 1.800ns 1.200ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "20.400 ns" { clock clk_1u led_convertor:display_component|clk_1k led_convertor:display_component|enb led_convertor:display_component|convertor:my_convert|b6[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "20.400 ns" { clock clock~out clk_1u led_convertor:display_component|clk_1k led_convertor:display_component|enb led_convertor:display_component|convertor:my_convert|b6[1] } { 0.000ns 0.000ns 2.500ns 4.600ns 3.300ns 3.900ns } { 0.000ns 2.800ns 1.100ns 1.100ns 1.100ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "system1" "UNKNOWN" "V1" "D:/altera/my vhdl file/system1/db/system1.quartus_db" { Floorplan "D:/altera/my vhdl file/system1/" "" "21.300 ns" { clock clk_1u led_convertor:display_component|clk_1k led_convertor:display_component|enb led_convertor:display_component|convertor:my_convert|temp5[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "21.300 ns" { clock clock~out clk_1u led_convertor:display_component|clk_1k led_convertor:display_component|enb led_convertor:display_component|convertor:my_convert|temp5[0] } { 0.000ns 0.000ns 2.500ns 4.600ns 3.300ns 4.800ns } { 0.000ns 2.800ns 1.100ns 1.100ns 1.100ns 0.000ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clock 77 " "Warning: Circuit may not operate. Detected 77 non-operational path(s) clocked by clock \"clock\" with clock skew larger than data delay. See Compilation Report for details." { } { } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -