system1.tan.summary

用VHDL语言实现的控制DS18B20构成测温仪表的程序

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 2.800 ns
From           : dq[0]
To             : \Reset1:present
From Clock     : --
To Clock       : clock
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 25.000 ns
From           : led_convertor:display_component|bitvector[0]
To             : bitvector[0]
From Clock     : clock
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 4.000 ns
From           : dq[0]
To             : \Reset1:buf[7]
From Clock     : --
To Clock       : clock
Failed Paths   : 0

Type           : Clock Setup: 'clock'
Slack          : N/A
Required Time  : None
Actual Time    : 15.38 MHz ( period = 65.000 ns )
From           : led_convertor:display_component|convertor:my_convert|temp5[0]
To             : led_convertor:display_component|convertor:my_convert|b6[1]
From Clock     : clock
To Clock       : clock
Failed Paths   : 0

Type           : Clock Hold: 'clock'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : ramdata[4]
To             : led_convertor:display_component|convertor:my_convert|temp4[3]
From Clock     : clock
To Clock       : clock
Failed Paths   : 77

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 77

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