led_convertor.vhd

用VHDL语言实现的控制DS18B20构成测温仪表的程序

--测温仪表的数制转换及显示模块
--硬件测试：通过
--作者；Michael
--时间：2006.10.20
--版本：定稿版

Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

Entity led_convertor is
	Port(clock:in std_logic;   --1MHz输入时钟
		 gate:in std_logic;    --是否更新显示的门控信号
		 temperaturein:in std_logic_vector(10 downto 0);  --温度数据
		 bitvector:out std_logic_vector(7 downto 0);  --数码管段选信号
		 wordselect:out std_logic_vector(5 downto 0)); --数码管位选信号
End entity led_convertor;
Architecture rtl of led_convertor is
	--定义了用于转换和显示的状态机的状态
	type statetype is(clear,enable,display);
	signal state:statetype :=clear;
	
	--数码管动态扫描时钟
	signal clk_1k:std_logic;
	
	--显示数字的轮巡变量
	signal mydata:integer range 0 to 9 ;
	
	--与数制转换器的接口信号
	signal w1,w2,w3:integer range 0 to 9 ;
	signal w4,w5,w6:integer range 0 to 9 ;
	signal clr,enb:std_logic :='0';
	
	--元件声明，数位转换器
	COMPONENT convertor 	
	Port(indata:in std_logic_vector(10 downto 0);
	 	 clear:in std_logic :='0';
		 enable:in std_logic :='0';
		 b6,b5,b4:out integer range 0 to 9;
		 b3,b2,b1:out integer range 0 to 9);
	END COMPONENT;
		
Begin
	
--数制转换器的元件例化	
my_convert: convertor
	PORT MAP(temperaturein,clr,enb,
			 w6,w5,w4,w3,w2,w1);
			
--分频器,由1MHz产生近似1KHz的扫描时钟信号				
mydivider:Process(clock,clk_1k)
	variable temp0:integer range 0 to 250 :=0;
	Begin 
		if(clock'event and clock='1') then 
			if(temp0=250) then 
				temp0:=0;
				clk_1k<=not clk_1k;
			else 
				temp0:=temp0+1;
			end if;
		end if;
	End Process;
	
--控制数制转换和显示的进程
myled:Process(clk_1k)
	variable temp0:integer range 0 to 6;
	variable temp1:integer range 0 to 5 :=5;
	variable temp2:std_logic_vector(6 downto 0);
	Begin
		if(clk_1k'event and clk_1k='1') then
			case state is
			when clear =>
						 if(temp0=1) then
							state<=enable;
							temp0:=0;
							clr<='0';
						 else
							state<=clear;
							temp0:=temp0+1;
							clr<='1';
						 end if;
			when enable =>
						 if(temp0=1) then
							state<=display;
							temp0:=0;
							enb<='0';
						 else
							state<=enable;
							temp0:=temp0+1;
							enb<='1';
						 end if;	
			when display =>	
							if(gate'event and gate='1') then
								state<=clear;
							end if;
							
							if (temp1=5) then 
								temp1:=0;
							else temp1:=temp1+1;
							end if;
							case temp1 is
								when 0 => wordselect<="011111";mydata<=w6;bitvector(7)<='0';
								when 1 => wordselect<="111110";mydata<=w5;bitvector(7)<='0';
								when 2 => wordselect<="111101";mydata<=w4;bitvector(7)<='1';
								when 3 => wordselect<="111011";mydata<=w3;bitvector(7)<='0';
								when 4 => wordselect<="110111";mydata<=w2;bitvector(7)<='0';
								when 5 => wordselect<="101111";mydata<=w1;bitvector(7)<='0';
							end case;
							case  mydata is
								when 0 => temp2:="0111111"; --0
								when 1 => temp2:="0000110";
								when 2 => temp2:="1011011";
								when 3 => temp2:="1001111";
								when 4 => temp2:="1100110";
								when 5 => temp2:="1101101";
								when 6 => temp2:="1111101";
								when 7 => temp2:="0000111";
								when 8 => temp2:="1111111";
								when 9 => temp2:="1101111";  --9
							end case;
							
							bitvector(6 downto 0)<=temp2;
			end case;
		end if;
	end process;
end rtl;