system1.map.summary

用VHDL语言实现的控制DS18B20构成测温仪表的程序

Analysis & Synthesis Status : Successful - Fri Oct 27 10:24:22 2006
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : system1
Top-level Entity Name : system1
Family : FLEX10K
Total logic elements : 490
Total pins : 24
Total memory bits : 0