system1.map.rpt

用VHDL语言实现的控制DS18B20构成测温仪表的程序

Analysis & Synthesis report for system1
Fri Oct 27 10:24:22 2006
Version 5.1 Build 176 10/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. State Machine - |system1|allstate
  8. State Machine - |system1|led_convertor:display_component|fsm3
  9. State Machine - |system1|led_convertor:display_component|state
 10. General Register Statistics
 11. Parameter Settings for User Entity Instance: lpm_bustri:lpm_bustri_component
 12. Parameter Settings for Inferred Entity Instance: lpm_add_sub:add_rtl_0
 13. Parameter Settings for Inferred Entity Instance: lpm_add_sub:add_rtl_1
 14. Parameter Settings for Inferred Entity Instance: led_convertor:display_component|lpm_add_sub:add_rtl_2
 15. Parameter Settings for Inferred Entity Instance: led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_3
 16. Parameter Settings for Inferred Entity Instance: led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_4
 17. Parameter Settings for Inferred Entity Instance: led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_5
 18. Parameter Settings for Inferred Entity Instance: led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_6
 19. Parameter Settings for Inferred Entity Instance: led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_7
 20. Parameter Settings for Inferred Entity Instance: led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_8
 21. Parameter Settings for Inferred Entity Instance: led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_9
 22. Parameter Settings for Inferred Entity Instance: led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_10
 23. Parameter Settings for Inferred Entity Instance: led_convertor:display_component|convertor:my_convert|lpm_add_sub:add_rtl_11
 24. Analysis & Synthesis Equations
 25. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Fri Oct 27 10:24:22 2006    ;
; Quartus II Version          ; 5.1 Build 176 10/26/2005 SJ Full Version ;
; Revision Name               ; system1                                  ;
; Top-level Entity Name       ; system1                                  ;
; Family                      ; FLEX10K                                  ;
; Total logic elements        ; 490                                      ;
; Total pins                  ; 24                                       ;
; Total memory bits           ; 0                                        ;
+-----------------------------+------------------------------------------+


+---------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                               ;
+------------------------------------------------------------+----------------+---------------+
; Option                                                     ; Setting        ; Default Value ;
+------------------------------------------------------------+----------------+---------------+
; Device                                                     ; EPF10K10LC84-4 ;               ;
; Top-level entity name                                      ; system1        ; system1       ;
; Family name                                                ; FLEX10K        ; Stratix       ;
; Use smart compilation                                      ; Off            ; Off           ;
; Create Debugging Nodes for IP Cores                        ; Off            ; Off           ;
; Preserve fewer node names                                  ; On             ; On            ;
; Disable OpenCore Plus hardware evaluation                  ; Off            ; Off           ;
; Verilog Version                                            ; Verilog_2001   ; Verilog_2001  ;
; VHDL Version                                               ; VHDL93         ; VHDL93        ;
; State Machine Processing                                   ; Auto           ; Auto          ;
; Extract Verilog State Machines                             ; On             ; On            ;
; Extract VHDL State Machines                                ; On             ; On            ;
; Add Pass-Through Logic to Inferred RAMs                    ; On             ; On            ;
; NOT Gate Push-Back                                         ; On             ; On            ;
; Power-Up Don't Care                                        ; On             ; On            ;
; Remove Redundant Logic Cells                               ; Off            ; Off           ;
; Remove Duplicate Registers                                 ; On             ; On            ;
; Ignore CARRY Buffers                                       ; Off            ; Off           ;
; Ignore CASCADE Buffers                                     ; Off            ; Off           ;
; Ignore GLOBAL Buffers                                      ; Off            ; Off           ;
; Ignore ROW GLOBAL Buffers                                  ; Off            ; Off           ;
; Ignore LCELL Buffers                                       ; Off            ; Off           ;
; Ignore SOFT Buffers                                        ; On             ; On            ;