ncelab.log

256Mbits (x8) 528 Bytes Page, NAND Flash Memory Verilog HDL Model User Manual

ncelab: 05.10-p004: (c) Copyright 1995-2003 Cadence Design Systems, Inc.
TOOL:	ncelab	05.10-p004: Started on Feb 03, 2005 at 16:49:11
ncelab
    -work worklib
    -cdslib cds.lib
    -hdlvar hdl.var
    -messages
    -nowarn
    -IEEE1364
    worklib.test_bench
    -access +r

	Elaborating the design hierarchy:
		Caching library 'worklib' ....... Done
	Building instance overlay tables: .................... Done
	Generating native compiled code:
		worklib.NAND256R3A:module <0x0a8a4b4a>
			streams: 234, words: 119101
		worklib.NAND_DRV:module <0x00e25a96>
			streams:  12, words: 71844
	Loading native compiled code:     .................... Done
	Building instance specific data structures.
	Design hierarchy summary:
		                 Instances  Unique
		Modules:                 3       3
		Resolved nets:           0       1
		Registers:             101     101
		Scalar wires:           28       -
		Vectored wires:          5       -
		Always blocks:          44      44
		Initial blocks:          2       2
		Cont. assignments:      24      24
		Pseudo assignments:      0      11
		Simulation timescale:  1ns
	Writing initial simulation snapshot: worklib.test_bench:module
TOOL:	ncelab	05.10-p004: Exiting on Feb 03, 2005 at 16:49:12  (total: 00:00:01)